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| author | Andrew Waterman <aswaterman@gmail.com> | 2018-07-09 15:51:54 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-09 15:51:54 -0700 |
| commit | 4dc3fa254ccc54e6f090722810506602ea59dbce (patch) | |
| tree | 9b36cdbca8ebfff093edb8d7087f34d3c196e4c8 /src | |
| parent | 14257efc74521936c9d465a0aa6c22a2f419920e (diff) | |
| download | riscv-isa-manual-4dc3fa254ccc54e6f090722810506602ea59dbce.zip riscv-isa-manual-4dc3fa254ccc54e6f090722810506602ea59dbce.tar.gz riscv-isa-manual-4dc3fa254ccc54e6f090722810506602ea59dbce.tar.bz2 | |
Make JALR assembly format consistent with binutils (#209)
Addresses #145
Diffstat (limited to 'src')
| -rw-r--r-- | src/assembly.tex | 10 | ||||
| -rw-r--r-- | src/c.tex | 4 | ||||
| -rw-r--r-- | src/rv32.tex | 4 |
3 files changed, 9 insertions, 9 deletions
diff --git a/src/assembly.tex b/src/assembly.tex index 98e6a41..ce48f75 100644 --- a/src/assembly.tex +++ b/src/assembly.tex @@ -96,13 +96,13 @@ pseudoinstruction & Base Instruction(s) & Meaning \\ \hline \hline {\tt j offset} & {\tt jal x0, offset} & Jump \\ {\tt jal offset} & {\tt jal x1, offset} & Jump and link \\ -{\tt jr rs} & {\tt jalr x0, rs, 0} & Jump register \\ -{\tt jalr rs} & {\tt jalr x1, rs, 0} & Jump and link register \\ -{\tt ret} & {\tt jalr x0, x1, 0} & Return from subroutine \\ +{\tt jr rs} & {\tt jalr x0, 0(rs)} & Jump register \\ +{\tt jalr rs} & {\tt jalr x1, 0(rs)} & Jump and link register \\ +{\tt ret} & {\tt jalr x0, 0(x1)} & Return from subroutine \\ \tt call offset & {\tt auipc x1, ${\tt offset[31:12]} + {\tt offset[11]}$} & Call far-away subroutine \\ - & {\tt jalr x1, x1, offset[11:0]} & \\ + & {\tt jalr x1, offset[11:0](x1)} & \\ \tt tail offset & {\tt auipc x6, ${\tt offset[31:12]} + {\tt offset[11]}$} & Tail call far-away subroutine \\ - & {\tt jalr x0, x6, offset[11:0]} & \\ + & {\tt jalr x0, offset[11:0](x6)} & \\ \hline {\tt fence} & {\tt fence iorw, iorw} & Fence on all memory and I/O \\ \hline @@ -673,12 +673,12 @@ C.JALR & src$\neq$0 & 0 & C2 \\ These instructions use the CR format. C.JR (jump register) performs an unconditional control transfer to -the address in register {\em rs1}. C.JR expands to {\tt jalr x0, rs1, 0}. +the address in register {\em rs1}. C.JR expands to {\tt jalr x0, 0(rs1)}. C.JALR (jump and link register) performs the same operation as C.JR, but additionally writes the address of the instruction following the jump ({\tt pc}+2) to the link register, {\tt x1}. C.JALR expands to -{\tt jalr x1, rs1, 0}. +{\tt jalr x1, 0(rs1)}. \begin{commentary} Strictly speaking, C.JALR does not expand exactly to a base RVI diff --git a/src/rv32.tex b/src/rv32.tex index b17e603..deda92c 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -797,8 +797,8 @@ When two different link registers ({\tt x1} and {\tt x5}) are given as support coroutines. If {\em rs1} and {\em rd} are the same link register (either {\tt x1} or {\tt x5}), the RAS is only pushed to enable macro-op fusion of the sequences:\linebreak -{\tt lui ra, imm20; jalr ra, ra, imm12} \ and \ -{\tt auipc ra, imm20; jalr ra, ra, imm12} +{\tt lui ra, imm20; jalr ra, imm12(ra)} \ and \ +{\tt auipc ra, imm20; jalr ra, imm12(ra)} \end{commentary} \subsubsection*{Conditional Branches} |