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| author | Andrew Waterman <andrew@sifive.com> | 2023-07-12 13:36:48 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-07-12 13:40:16 -0700 |
| commit | 6307d2c9d223649c315b728a40d392899e3f0c8a (patch) | |
| tree | 60fd8fbf132aea82e5d95e7b0f5060d158d85e75 /src/c-st-ext.adoc | |
| parent | 8631b79db26cb338cb2b697e5afeb1350396df51 (diff) | |
| download | riscv-isa-manual-6307d2c9d223649c315b728a40d392899e3f0c8a.zip riscv-isa-manual-6307d2c9d223649c315b728a40d392899e3f0c8a.tar.gz riscv-isa-manual-6307d2c9d223649c315b728a40d392899e3f0c8a.tar.bz2 | |
RV64E cleanup
Diffstat (limited to 'src/c-st-ext.adoc')
| -rw-r--r-- | src/c-st-ext.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index 8e260d2..c488af1 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -185,7 +185,7 @@ ADDI4SPN instruction. The RISC-V ABI was changed to make the frequently used registers map to registers 'x8-x15'. This simplifies the decompression decoder by having a contiguous naturally aligned set of register numbers, and is -also compatible with the RV32E and RV64E base ISA, which only have 16 integer +also compatible with the RV32E and RV64E base ISAs, which only have 16 integer registers. ==== Compressed register-based floating-point loads and stores also use the |