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| author | kanataso <kanapo.go@gmail.com> | 2023-07-12 23:25:35 +0900 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-07-12 13:40:16 -0700 |
| commit | 8631b79db26cb338cb2b697e5afeb1350396df51 (patch) | |
| tree | 86fb14560bc1f749ac5eef4f9c051561101562d6 /src/c-st-ext.adoc | |
| parent | 88f0547851943bdfd2f20ce29528b7030afee360 (diff) | |
| download | riscv-isa-manual-8631b79db26cb338cb2b697e5afeb1350396df51.zip riscv-isa-manual-8631b79db26cb338cb2b697e5afeb1350396df51.tar.gz riscv-isa-manual-8631b79db26cb338cb2b697e5afeb1350396df51.tar.bz2 | |
Add RV64E to Base Integer ISA
RV32E and RV64E Base Integer Instruction Sets is Ratified.
Signed-off-by: kanataso <kanapo.go@gmail.com>
Diffstat (limited to 'src/c-st-ext.adoc')
| -rw-r--r-- | src/c-st-ext.adoc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index feba7f8..8e260d2 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -76,7 +76,7 @@ integer loads and stores. ==== RVC was designed under the constraint that each RVC instruction expands -into a single 32-bit instruction in either the base ISA (RV32I/E, RV64I, +into a single 32-bit instruction in either the base ISA (RV32I/E, RV64I/E, or RV128I) or the F and D standard extensions where present. Adopting this constraint has two main benefits: @@ -185,7 +185,7 @@ ADDI4SPN instruction. The RISC-V ABI was changed to make the frequently used registers map to registers 'x8-x15'. This simplifies the decompression decoder by having a contiguous naturally aligned set of register numbers, and is -also compatible with the RV32E base ISA, which only has 16 integer +also compatible with the RV32E and RV64E base ISA, which only have 16 integer registers. ==== Compressed register-based floating-point loads and stores also use the |