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| author | Andrew Waterman <andrew@sifive.com> | 2024-06-10 18:01:17 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-06-10 18:01:17 -0700 |
| commit | e9704f3cff9e91277aca1045b37330a8f692deeb (patch) | |
| tree | 6b29eaa5273d5fda26fa6d19a17cda9075cde99d | |
| parent | ad0a305aea6aebda7e26e857886143bb38928f4c (diff) | |
| download | riscv-isa-manual-e9704f3cff9e91277aca1045b37330a8f692deeb.zip riscv-isa-manual-e9704f3cff9e91277aca1045b37330a8f692deeb.tar.gz riscv-isa-manual-e9704f3cff9e91277aca1045b37330a8f692deeb.tar.bz2 | |
Add note that vsstatus.FS/VS deviate from the HS-qualified rule
This isn't a change; it's just a repetition of the information in
the vsstatus register section.
| -rw-r--r-- | src/hypervisor.adoc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 85cb67f..959af02 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -2061,6 +2061,19 @@ Because TSR and TVM in `mstatus` are intended to impact only S-mode (HS-mode), they are ignored for determining exceptions in VS-mode. ==== +Fields FS and VS in registers `sstatus` and `vsstatus` deviate from the usual +_HS-qualified_ rule. +If an instruction is prevented from executing because FS or VS is zero in +either `sstatus` or `vsstatus`, the exception raised is always an +illegal-instruction exception, never a virtual-instruction exception. + +[NOTE] +==== +Early implementations of the H extension treated FS and VS in `sstatus` and +`vsstatus` specially this way, and the behavior has been codified to maintain +compatibility for software. +==== + <<< [[HSyncExcPrio]] |