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| author | Bill Traynor <wmat@riscv.org> | 2022-11-22 15:32:08 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2022-11-22 15:32:08 -0500 |
| commit | bad02d7c01acbd8d98d3d9e5f37f0a0d42f2b48c (patch) | |
| tree | 12626f17bad5fd719a6a90953ee44f769aeb5c23 | |
| parent | 2d9f900da540a12438dc2545c4882178a2b5a485 (diff) | |
| download | riscv-isa-manual-bad02d7c01acbd8d98d3d9e5f37f0a0d42f2b48c.zip riscv-isa-manual-bad02d7c01acbd8d98d3d9e5f37f0a0d42f2b48c.tar.gz riscv-isa-manual-bad02d7c01acbd8d98d3d9e5f37f0a0d42f2b48c.tar.bz2 | |
Formatting table to fix right column.
Trying to get the formatting of the table so right column
content doesn't wrap weirdly.
| -rw-r--r-- | src/intro.adoc | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/src/intro.adoc b/src/intro.adoc index eab1837..0859f64 100644 --- a/src/intro.adoc +++ b/src/intro.adoc @@ -445,7 +445,7 @@ encoding scheme is designed to support ISA extensions with variable-length instructions, where each instruction can be any number of 16-bit instruction _parcels_ in length and parcels are naturally aligned on 16-bit boundaries. The standard compressed ISA extension -described in <<compressed>> reduces code size by +described in <<compressed, Chapter 18>> reduces code size by providing compressed 16-bit instructions and relaxes the alignment constraints to allow all instructions (16 bit and 32 bit) to be aligned on any 16-bit boundary to improve code density. @@ -463,7 +463,7 @@ multiple of IALIGN. For implementations supporting only a base instruction set, ILEN is 32 bits. Implementations supporting longer instructions have larger values of ILEN. -<<instlengthcode>> illustrates the standard +<<instlengthcode, Table 1>> illustrates the standard RISC-V instruction-length encoding convention. All the 32-bit instructions in the base ISA have their lowest two bits set to "11". The optional compressed 16-bit instruction-set extensions have their lowest @@ -487,24 +487,26 @@ between 80 bits and 176 bits are encoded using a 3-bit field in bits "111" is reserved for future longer instruction encodings. [[instlengthcode]] -.RISC-V instruction length encoding. Only the 16-bit and 32-bit encodings are considered frozen at this time. -[cols="^2,^4,^3,^3,<2",] +.RISC-V instruction length encoding. + +Only the 16-bit and 32-bit encodings are considered frozen at this time. +[%autowidth,cols="^2,^2,^3,^3,<4"] |=== -| | | |`xxxxxxxxxxxxxxaa` |16-bit (`aa`≠`11`) +||||xxxxxxxxxxxxxxaa |16-bit (aa≠11) -| | |`xxxxxxxxxxxxxxxx` |`xxxxxxxxxxxbbb11` |32-bit (`bbb`≠`111`) +|||xxxxxxxxxxxxxxxx |xxxxxxxxxxxbbb11 |32-bit (bbb≠111) -| |latexmath:[$\cdot\cdot\cdot$]`xxxx` |`xxxxxxxxxxxxxxxx` -|`xxxxxxxxxx011111` |48-bit +||latexmath:[$\cdot\cdot\cdot$]xxxx |xxxxxxxxxxxxxxxx +|xxxxxxxxxx011111 |48-bit -| |latexmath:[$\cdot\cdot\cdot$]`xxxx` |`xxxxxxxxxxxxxxxx` -|`xxxxxxxxx0111111` |64-bit +||latexmath:[$\cdot\cdot\cdot$]xxxx |xxxxxxxxxxxxxxxx +|xxxxxxxxx0111111 |64-bit -| |latexmath:[$\cdot\cdot\cdot$]`xxxx` |`xxxxxxxxxxxxxxxx` -|`xnnnxxxxx1111111` |(80+16*`nnn`)-bit, `nnn`≠`111` +||latexmath:[$\cdot\cdot\cdot$]xxxx |xxxxxxxxxxxxxxxx +|xnnnxxxxx1111111 |(80+16*nnn)-bit, nnn≠111 -| |latexmath:[$\cdot\cdot\cdot$]`xxxx` |`xxxxxxxxxxxxxxxx` -|`x111xxxxx1111111` |Reserved for ≥192-bits +||latexmath:[$\cdot\cdot\cdot$]xxxx |xxxxxxxxxxxxxxxx +|x111xxxxx1111111 |Reserved for ≥192-bits |Byte Address: |base+4 |base+2 |base | |=== |