diff options
| author | Bill Traynor <wmat@riscv.org> | 2022-11-22 14:59:29 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2022-11-22 14:59:29 -0500 |
| commit | 2d9f900da540a12438dc2545c4882178a2b5a485 (patch) | |
| tree | c835c39324e1e39ed81b3a3dac3248e0a371c78c | |
| parent | af1679056fceb2c8f3b87f1bf190ea7c1d7929c8 (diff) | |
| download | riscv-isa-manual-2d9f900da540a12438dc2545c4882178a2b5a485.zip riscv-isa-manual-2d9f900da540a12438dc2545c4882178a2b5a485.tar.gz riscv-isa-manual-2d9f900da540a12438dc2545c4882178a2b5a485.tar.bz2 | |
Adding custom text for xref to table.
Trying to shorten the displayed text when a table is referenced.
| -rw-r--r-- | src/intro.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intro.adoc b/src/intro.adoc index b0bcd54..eab1837 100644 --- a/src/intro.adoc +++ b/src/intro.adoc @@ -480,7 +480,7 @@ instructions longer than 32 bits is not considered frozen. Standard instruction-set extensions encoded with more than 32 bits have additional low-order bits set to "1", with the conventions for 48-bit and 64-bit lengths shown in -<<instlengthcode>>. Instruction lengths +<<instlengthcode, Table 1>>. Instruction lengths between 80 bits and 176 bits are encoded using a 3-bit field in bits [14:12] giving the number of 16-bit words in addition to the first 5latexmath:[$\times$]16-bit words. The encoding with bits [14:12] set to |