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author | Andrew Waterman <andrew@sifive.com> | 2024-01-29 23:22:08 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2024-01-30 15:59:02 -0800 |
commit | adf708ce29ff5d93a8588ac026df72ed8e57b06f (patch) | |
tree | 7ebd05705719a3fe721463a4ff58b0e59e275e95 | |
parent | 1fbfde35e12501dfbd3dc634e8725f425beaa6fa (diff) | |
download | riscv-isa-manual-adf708ce29ff5d93a8588ac026df72ed8e57b06f.zip riscv-isa-manual-adf708ce29ff5d93a8588ac026df72ed8e57b06f.tar.gz riscv-isa-manual-adf708ce29ff5d93a8588ac026df72ed8e57b06f.tar.bz2 |
Add changelog entry
-rw-r--r-- | src/priv-preface.adoc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc index 4591c9f..f7e9a07 100644 --- a/src/priv-preface.adoc +++ b/src/priv-preface.adoc @@ -11,9 +11,11 @@ modules: |_Machine ISA_ + _Supervisor ISA_ + _Smrnmi Extension_ + +*Svade Extension* + *Svnapot Extension* + *Svpbmt Extension* + *Svinval Extension* + +*Svadu Extension* + *Hypervisor ISA* |_1.13_ + _1.13_ + @@ -21,6 +23,8 @@ _0.1_ + *1.0* + *1.0* + *1.0* + +*1.0* + +*1.0* + *1.0* |_Draft_ + _Draft_ + @@ -28,6 +32,8 @@ _Draft_ + *Ratified* + *Ratified* + *Ratified* + +*Ratified* + +*Ratified* + *Ratified* |=== @@ -50,6 +56,7 @@ implemented. * Defined hardware error and software check exception codes. * Specified synchronization requirements when changing the PBMTE fields in `menvcfg` and `henvcfg`. +* Incorporated Svade and Svadu extension specifications. * Clarified that "platform- or custom-use" interrupts are actually "platform-use interrupts", where the platform can choose to make some custom. * Clarified semantics of explicit accesses to CSRs wider than XLEN bits. |