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| author | Andrew Waterman <andrew@sifive.com> | 2024-01-29 22:32:29 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-01-30 15:59:02 -0800 |
| commit | 1fbfde35e12501dfbd3dc634e8725f425beaa6fa (patch) | |
| tree | 6f00a2b036ae39d22efe0b65b863c6b3d30057d9 | |
| parent | 4fb0e6a7229792279a32fb62f166e370b21526c4 (diff) | |
| download | riscv-isa-manual-1fbfde35e12501dfbd3dc634e8725f425beaa6fa.zip riscv-isa-manual-1fbfde35e12501dfbd3dc634e8725f425beaa6fa.tar.gz riscv-isa-manual-1fbfde35e12501dfbd3dc634e8725f425beaa6fa.tar.bz2 | |
Add Svadu chapter
| -rw-r--r-- | src/hypervisor.adoc | 1 | ||||
| -rw-r--r-- | src/machine.adoc | 1 | ||||
| -rw-r--r-- | src/supervisor.adoc | 15 |
3 files changed, 17 insertions, 0 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index c7944b8..6d3d226 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -570,6 +570,7 @@ cause a supervisor-level (HS-level) guest external interrupt. The enable bits in `hgeie` do not affect the VS-level external interrupt signal selected from `hgeip` by `hstatus`.VGEIN. +[[sec:henvcfg]] ==== Hypervisor Environment Configuration Register (`henvcfg`) The `henvcfg` CSR is a 64-bit read/write register, formatted diff --git a/src/machine.adoc b/src/machine.adoc index c12ebda..0469a15 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -1969,6 +1969,7 @@ of a memory-mapped register that is programmed by the platform or by M-mode software towards the beginning of the boot process. ==== +[[sec:menvcfg]] ==== Machine Environment Configuration Register (`menvcfg`) The `menvcfg` CSR is a 64-bit read/write register, formatted diff --git a/src/supervisor.adoc b/src/supervisor.adoc index 76dab3f..85f0ec2 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -2030,3 +2030,18 @@ HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR instructions as no-ops. ==== + +[[sec:svadu]] +== "Svadu" Standard Extension for Hardware Updating of A/D Bits, Version 1.0 + +The Svadu extension adds support and CSR controls for hardware updating of PTE A/D bits. + +If the Svadu extension is implemented, the `menvcfg`.ADUE field is writable. +If the hypervisor extension is additionally implemented, the `henvcfg`.ADUE +field is also writable. +See <<sec:menvcfg>> and <<sec:henvcfg>> for the definitions of those fields. + +<<translation>> defines the semantics of hardware updating of A/D bits. When +hardware updating of A/D bits is disabled, the Svade extension, which mandates +exceptions when A/D bits need be set, instead takes effect. +The Svade extension is also defined in <<translation>>. |