Merge pull request #1357 from riscv/kersten1-patch-4riscv-isa-release-aa0572c-2024-04-24

More register name clean up

2 files changed, 44 insertions, 44 deletions

diff --git a/src/machine.adoc b/src/machine.adoc
index 7e4e15c..f778de5 100644
--- a/src/machine.adoc
+++ b/src/machine.adoc
@@ -53,7 +53,7 @@ knowing the register width (MXLEN) of the hart. The base width is
 given by __MXLEN=2^MXL+4^__.
 
 The base width can also be found if `misa` is zero, by placing the
-immediate 4 in a register then shifting the register left by 31 bits at
+immediate 4 in a register, then shifting the register left by 31 bits at
 a time. If zero after one shift, then the hart is RV32. If zero after
 two shifts, then the hart is RV64, else RV128.
 ====
@@ -285,7 +285,7 @@ is not implemented. The combination of `mvendorid` and `marchid` should
 uniquely identify the type of hart microarchitecture that is
 implemented.
 
-.Machine Architecture ID register (`marchid`)
+.Machine Architecture ID (`marchid`) register 
 include::images/bytefield/marchid.adoc[]
 
 Open-source project architecture IDs are allocated globally by RISC-V
@@ -323,7 +323,7 @@ implementation, but a value of 0 can be returned to indicate that the
 field is not implemented. The Implementation value should reflect the
 design of the RISC-V processor itself and not any surrounding system.
 
-.Machine Implementation ID register (`mimpid`)
+.Machine Implementation ID (`mimpid`) register 
 include::images/bytefield/mimpid.adoc[]
 
 [NOTE]
@@ -345,7 +345,7 @@ numbered contiguously in a multiprocessor system, but at least one hart
 must have a hart ID of zero. Hart IDs must be unique within the
 execution environment.
 
-.Hart ID register (`mhartid`)
+.Hart ID (`mhartid`) register 
 include::images/bytefield/mhartid.adoc[]
 
 [NOTE]
@@ -367,12 +367,12 @@ restricted view of `mstatus` appears as the `sstatus` register in the
 S-level ISA.
 
 [[mstatusreg-rv32]]
-.Machine-mode status register (`mstatus`) for RV32
+.Machine-mode status (`mstatus`) register for RV32
 include::images/bytefield/mstatusreg-rv32.adoc[]
 
 include::images/bytefield/mstatusreg.adoc[]
 [[mstatusreg]]
-.Machine-mode status register (`mstatus`) for RV64
+.Machine-mode status (`mstatus`) register for RV64
 include::images/bytefield/mstatusreg2.adoc[]
 
 
@@ -380,7 +380,7 @@ For RV32 only, `mstatush` is a 32-bit read/write register formatted as
 shown in <<mstatushreg>>. Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.
 
 [[mstatushreg]]
-.Additional machine-mode status register (`mstatush`) for RV32.
+.Additional machine-mode status (`mstatush`) register  for RV32.
 include::images/bytefield/mstatushreg.adoc[]
 
 [[privstack]]
@@ -1142,7 +1142,7 @@ implementations can provide individual read/write bits within `medeleg`
 and `mideleg` to indicate that certain exceptions and interrupts should
 be processed directly by a lower privilege level. The machine exception
 delegation register (`medeleg`) is a 64-bit read/write register.
-The machine interrupt delegation register (`mideleg`) is an MXLEN-bit
+The machine interrupt delegation (`mideleg`) register is an MXLEN-bit
 read/write register.
 
 In harts with S-mode, the `medeleg` and `mideleg` registers must
@@ -1202,7 +1202,7 @@ will not be taken when executing in M-mode. By contrast, if `mideleg`[5]
 is clear, STIs can be taken in any mode and regardless of current mode
 will transfer control to M-mode.
 
-.Machine Exception Delegation Register `medeleg`.
+.Machine Exception Delegation (`medeleg`) register.
 include::images/bytefield/medeleg.adoc[]
 
 `medeleg` has a bit position allocated for every synchronous exception
@@ -1213,9 +1213,9 @@ lower-privilege trap handler).
 
 When XLEN=32, `medelegh` is a 32-bit read/write register
 that aliases bits 63:32 of `medeleg`.
-Register `medelegh` does not exist when XLEN=64.
+The `medelegh` register does not exist when XLEN=64.
 
-.Machine Interrupt Delegation Register `mideleg`.
+.Machine Interrupt Delegation (`mideleg`) Register.
 include::images/bytefield/mideleg.adoc[]
 
 `mideleg` holds trap delegation bits for individual interrupts, with the
@@ -1239,10 +1239,10 @@ bits 16 and above are designated for platform use.
 NOTE: Interrupts designated for platform use may be designated for custom use
 at the platform's discretion.
 
-.Machine Interrupt-Pending Register (mip).
+.Machine Interrupt-Pending (`mip`) register.
 include::images/bytefield/mideleg.adoc[]
 
-.Machine Interrupt-Enable Register (mie)
+.Machine Interrupt-Enable (`mie`) register
 include::images/bytefield/mideleg.adoc[]
 
 An interrupt _i_ will trap to M-mode (causing the privilege mode to
@@ -1272,7 +1272,7 @@ A bit in `mie` must be writable if the corresponding interrupt can ever
 become pending. Bits of `mie` that are not writable must be read-only
 zero.
 
-The standard portions (bits 15:0) of registers `mip` and `mie` are
+The standard portions (bits 15:0) of the `mip` and `mie` registers are
 formatted as shown in <<mipreg-standard>> and <<miereg-standard>> respectively.
 
 [[mipreg-standard]]
@@ -1304,7 +1304,7 @@ interrupt controller.
 
 Bits `mip`.MTIP and `mie`.MTIE are the interrupt-pending and
 interrupt-enable bits for machine timer interrupts. MTIP is read-only in
-`mip`, and is cleared by writing to the memory-mapped machine-mode timer
+the `mip` register, and is cleared by writing to the memory-mapped machine-mode timer
 compare register.
 
 Bits `mip`.MSIP and `mie`.MSIE are the interrupt-pending and
@@ -1454,11 +1454,11 @@ The `mhpmevent__n__h` CSRs are provided only if the Sscofpmf extension is implem
 [[mcounteren]]
 ==== Machine Counter-Enable (`mcounteren`) Register 
 
-The counter-enable register `mcounteren` is a 32-bit register that
+The counter-enable `mcounteren` register is a 32-bit register that
 controls the availability of the hardware performance-monitoring
 counters to the next-lower privileged mode.
 
-.Counter-enable register (`mcounteren`).
+.Counter-enable (`mcounteren`) register.
 include::images/bytefield/counteren.adoc[]
 
 The settings in this register only control accessibility. The act of
@@ -1506,7 +1506,7 @@ executing in a less-privileged mode. In harts without U-mode, the
 
 ==== Machine Counter-Inhibit (`mcountinhibit`) Register 
 
-.Counter-inhibit register `mcountinhibit`
+.Counter-inhibit `mcountinhibit` register
 include::images/bytefield/counterinh.adoc[]
 
 The counter-inhibit register `mcountinhibit` is a 32-bit *WARL* register that
@@ -1565,7 +1565,7 @@ design, the OS can rely on holding a value in the `mscratch` register
 while the user context is running.
 ====
 
-==== Machine Exception Program Counter (`mepc`)
+==== Machine Exception Program Counter (`mepc`) Register
 
 `mepc` is an MXLEN-bit read/write register formatted as shown in
 <<mepcreg>>. The low bit of `mepc` (`mepc[0]`) is
@@ -1617,7 +1617,7 @@ the possible machine-level exception codes. The Exception Code is a
 *WLRL* field, so is only guaranteed to hold supported exception codes.
 
 [[mcausereg]]
-.Machine Cause register `mcause`.
+.Machine Cause (`mcause`) register.
 include::images/bytefield/mcausereg.adoc[]
 
 Note that load and load-reserved instructions generate load exceptions,
@@ -1649,7 +1649,7 @@ synchronous exceptions is implementation-defined.
 <<<
 
 [[mcauses]]
-.Machine cause register (mcause) values after trap.
+.Machine cause (`mcause`) register values after trap.
 [%autowidth,float="center",align="center",cols=">,>,<",options="header",]
 |===
 |Interrupt |Exception Code |Description 
@@ -1889,7 +1889,7 @@ exceptions. This design reduces datapath cost for most implementations,
 particularly those with hardware page-table walkers.
 
 [[mtvalreg]]
-.Machine Trap Value register.
+.Machine Trap Value (`mtval`) register.
 include::images/bytefield/mtvalreg.adoc[]
 
 
@@ -1956,14 +1956,14 @@ _N_ is the smaller of MXLEN and ILEN.
 
 ==== Machine Configuration Pointer (`mconfigptr`) Register 
 
-`mconfigptr` is an MXLEN-bit read-only CSR, formatted as shown in
+The `mconfigptr` register is an MXLEN-bit read-only CSR, formatted as shown in
 <<mconfigptrreg>>, that holds the physical
 address of a configuration data structure. Software can traverse this
 data structure to discover information about the harts, the platform,
 and their configuration.
 
 [[mconfigptrreg]]
-.Machine Configuration Pointer register.
+.Machine Configuration Pointer (`mconfigptr`) register.
 include::images/bytefield/mconfigptrreg.adoc[]
 
 
@@ -1972,7 +1972,7 @@ i.e., if MXLEN is
 latexmath:[$8\times n$], then `mconfigptr`[latexmath:[$\log_2n$]-1:0]
 must be zero.
 
-`mconfigptr` must be implemented, but it may be zero to indicate the
+The `mconfigptr` register must be implemented, but it may be zero to indicate the
 configuration data structure does not exist or that an alternative
 mechanism must be used to locate it.
 
@@ -1983,7 +1983,7 @@ standardized.
 
 ***
 
-While `mconfigptr` will simply be hardwired in some implementations,
+While the `mconfigptr` register will simply be hardwired in some implementations,
 other implementations may provide a means to configure the value
 returned on CSR reads. For example, `mconfigptr` might present the value
 of a memory-mapped register that is programmed by the platform or by
@@ -1999,7 +1999,7 @@ certain characteristics of the execution environment for modes less
 privileged than M.
 
 [#menvcfgreg]
-.Machine environment configuration register (`menvcfg`).
+.Machine environment configuration (`menvcfg`) register.
 include::images/bytefield/menvcfgreg.adoc[]
 
 If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`,
@@ -2093,7 +2093,7 @@ ratification of that extension.
 
 When XLEN=32, `menvcfgh` is a 32-bit read/write register
 that aliases bits 63:32 of `menvcfg`.
-Register `menvcfgh` does not exist when XLEN=64.
+The `menvcfgh` register does not exist when XLEN=64.
 
 If U-mode is not supported, then registers `menvcfg` and `menvcfgh` do
 not exist.
@@ -2104,7 +2104,7 @@ not exist.
 shown in <<mseccfg>>, that controls security features.
 
 [[mseccfg]]
-.Machine security configuration register (`mseccfg`).
+.Machine security configuration (`mseccfg`) register.
 include::images/bytefield/mseccfg.adoc[]
 
 The definitions of the SSEED and USEED fields will be furnished by the
diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index a3ed6c4..3304257 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -46,13 +46,13 @@ register keeps track of the processor's current operating state.
 include::images/bytefield/sstatus32-1.edn[]
 
 [[sstatusreg-rv32]]
-.Supervisor-mode status register (`sstatus`) when SXLEN=32.
+.Supervisor-mode status (`sstatus`) register when SXLEN=32.
 include::images/bytefield/sstatus32-2.edn[]
 
 include::images/bytefield/sstatus64.edn[]
 
 [[sstatusreg]]
-.Supervisor-mode status register (`sstatus`) when SXLEN=64.
+.Supervisor-mode status (`sstatus`) register when SXLEN=64.
 include::images/bytefield/sstatus32-2.edn[]
 
 The SPP bit indicates the privilege level at which a hart was executing
@@ -182,7 +182,7 @@ The `stvec` register is an SXLEN-bit read/write register that holds trap
 vector configuration, consisting of a vector base address (BASE) and a
 vector mode (MODE).
 
-.Supervisor trap vector base address register (`stvec`).
+.Supervisor trap vector base address (`stvec`) register.
 include::images/bytefield/stvec.edn[]
 
 The BASE field in `stvec` is a  field that can hold any valid virtual or
@@ -338,10 +338,10 @@ interrupts in terms of the real-time counter, `time`.
 
 ==== Counter-Enable (`scounteren`) Register 
 
-.Counter-enable register (`scounteren`)
+.Counter-enable (`scounteren`) register
 include::images/bytefield/scounteren.edn[]
 
-The counter-enable register `scounteren` is a 32-bit register that
+The counter-enable (`scounteren`) CSR is a 32-bit register that
 controls the availability of the hardware performance monitoring
 counters to U-mode.
 
@@ -366,7 +366,7 @@ access a counter if the corresponding bits in `scounteren` and
 
 ==== Supervisor Scratch (`sscratch`) Register 
 
-The `sscratch` register is an SXLEN-bit read/write register, dedicated
+The `sscratch` CSR is an SXLEN-bit read/write register, dedicated
 for use by the supervisor. Typically, `sscratch` is used to hold a
 pointer to the hart-local supervisor context while the hart is executing
 user code. At the beginning of a trap handler, `sscratch` is swapped
@@ -377,7 +377,7 @@ include::images/bytefield/sscratch.edn[]
 
 ==== Supervisor Exception Program Counter (`sepc`) Register
 
-`sepc` is an SXLEN-bit read/write register formatted as shown in
+`sepc` is an SXLEN-bit read/write CSR formatted as shown in
 <<epcreg>>. The low bit of `sepc` (`sepc[0]`) is always zero. On implementations that support only IALIGN=32, the two low bits (`sepc[1:0]`) are always zero.
 
 If an implementation allows IALIGN to be either 16 or 32 (by changing
@@ -404,7 +404,7 @@ include::images/bytefield/epcreg.edn[]
 [[scause]]
 ==== Supervisor Cause (`scause`) Register 
 
-The `scause` register is an SXLEN-bit read-write register formatted as
+The `scause` CSR is an SXLEN-bit read-write register formatted as
 shown in <<scausereg>>. When a trap is taken into
 S-mode, `scause` is written with a code indicating the event that
 caused the trap. Otherwise, `scause` is never written by the
@@ -419,11 +419,11 @@ Exception Code is a *WLRL* field. It is required to hold the values 0–31
 guaranteed to hold supported exception codes.
 
 [[scausereg]]
-.Supervisor Cause register `scause`.
+.Supervisor Cause (`scause`) register.
 include::images/bytefield/scausereg.edn[]
 
 [[scauses]]
-.Supervisor cause register (`scause`) values after trap. Synchronous exception priorities are given by <<exception-priority>>.
+.Supervisor cause (`scause`) register values after trap. Synchronous exception priorities are given by <<exception-priority>>.
 [%autowidth,float="center",align="center",cols=">,>,3",options="header"]
 |===
 |Interrupt |Exception Code |Description
@@ -528,7 +528,7 @@ _Reserved_
 
 ==== Supervisor Trap Value (`stval`) Register
 
-The `stval` register is an SXLEN-bit read-write register formatted as
+The `stval` CSR is an SXLEN-bit read-write register formatted as
 shown in <<stvalreg>>. When a trap is taken into
 S-mode, `stval` is written with exception-specific information to assist
 software in handling the trap. Otherwise, `stval` is never written by
@@ -673,7 +673,7 @@ ratification of that extension.
 [[satp]]
 ==== Supervisor Address Translation and Protection (`satp`) Register
 
-The `satp` register is an SXLEN-bit read/write register, formatted as
+The `satp` CSR is an SXLEN-bit read/write register, formatted as
 shown in <<rv32satp>> for SXLEN=32 and
 <<rv64satp>> for SXLEN=64, which controls
 supervisor-mode address translation and protection. This register holds
@@ -685,7 +685,7 @@ address-translation scheme. Further details on the access to this
 register are described in <<virt-control>>.
 
 [[rv32satp]]
-.Supervisor address translation and protection register `satp` when SXLEN=32.
+.Supervisor address translation and protection (`satp`) register when SXLEN=32.
 include::images/bytefield/rv32satp.edn[]
 
 [NOTE]
@@ -700,7 +700,7 @@ corresponding to main memory be representable.
 ====
 
 [[rv64satp]]
-.Supervisor address translation and protection register `satp` when SXLEN=64, for MODE values Bare, Sv39, Sv48, and Sv57.
+.Supervisor address translation and protection (`satp`) register when SXLEN=64, for MODE values Bare, Sv39, Sv48, and Sv57.
 include::images/bytefield/rv64satp.edn[]
 
 [NOTE]
@@ -820,7 +820,7 @@ inexpensive relative to the multi-level cache hierarchies whose address
 space they map.
 ====
 
-The `satp` register is considered _active_ when the effective privilege
+The `satp` CSR is considered _active_ when the effective privilege
 mode is S-mode or U-mode. Executions of the address-translation
 algorithm may only begin using a given value of `satp` when `satp` is
 active.