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author | Ved Shanbhogue <ved@rivosinc.com> | 2024-07-09 18:07:08 -0500 |
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committer | Ved Shanbhogue <ved@rivosinc.com> | 2024-07-09 18:07:08 -0500 |
commit | 604f9f91b774398ab2d52ab9ccd369c58dda30cf (patch) | |
tree | 412ddae3de939937e19a6377648f9c163f094bc2 | |
parent | 94c4194793036391dbb01db68071f26cb223513a (diff) | |
download | riscv-isa-manual-604f9f91b774398ab2d52ab9ccd369c58dda30cf.zip riscv-isa-manual-604f9f91b774398ab2d52ab9ccd369c58dda30cf.tar.gz riscv-isa-manual-604f9f91b774398ab2d52ab9ccd369c58dda30cf.tar.bz2 |
Clarify RNMI and Smdbltrp/Ssdbltrp interaction
-rw-r--r-- | src/machine.adoc | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/machine.adoc b/src/machine.adoc index 13d264d..a81f7bb 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -498,9 +498,11 @@ by the same write (For RV32, the `MDT` bit is in `mstatush` and the `MIE` bit in When a trap is to be taken into M-mode, if the `MDT` bit is currently 0, it is then set to 1, and the trap is delivered as expected. However, if `MDT` is -already set to 1, then this is an _unexpected trap_. Additionally, when the -Smrnmi extension is implemented, a trap that occurs when executing in M-mode -with the `mnstatus.NMIE` set to 0 is an _unexpected trap_. +already set to 1, then this is an _unexpected trap_. When the Smrnmi extension +is implemented, a trap caused by an RNMI is not considered an _unexpected trap_ +irrespective of the state of the `MDT` bit. A trap caused by an RNMI does not +set the `MDT` bit. However, a trap that occurs when executing in M-mode with +`mnstatus.NMIE` set to 0 is an _unexpected trap_. In the event of a _unexpected trap_, the handling is as follows: @@ -537,6 +539,10 @@ The `MRET` and `SRET` instructions, when executed in M-mode, set the `MDT` bit to 0. If the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set to 0. Additionally, if it is VU, then `vsstatus.SDT` is also set to 0. +The `MNRET` instruction, provided by the Smrnmi extension, sets the `MDT` bit to +0 if the new privilege mode is not M. If it is U, VS, or VU, then `sstatus.SDT` is +also set to 0. Additionally, if it is VU, then `vsstatus.SDT` is also set to 0. + [[xlen-control]] ===== Base ISA Control in `mstatus` Register |