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| author | Andrew Waterman <andrew@sifive.com> | 2019-10-11 15:49:27 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-10-11 15:49:27 -0700 |
| commit | 057366db9a4241d6e6ee2a711da7201b1993a2c4 (patch) | |
| tree | f2038114dea7d59e3bd5e5374d65a0f2d3824627 | |
| parent | 36d00c4e67699d4c661b3d2cc0eb3ac6db15c08c (diff) | |
| download | riscv-isa-manual-057366db9a4241d6e6ee2a711da7201b1993a2c4.zip riscv-isa-manual-057366db9a4241d6e6ee2a711da7201b1993a2c4.tar.gz riscv-isa-manual-057366db9a4241d6e6ee2a711da7201b1993a2c4.tar.bz2 | |
fix formatting
| -rw-r--r-- | src/supervisor.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 30156c5..3e6ec73 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1053,7 +1053,7 @@ memory locations, an SFENCE.VMA instruction must be executed after the writes to flush the relevant cached translations. Implementations must only perform implicit reads of the translation -data structures pointed to by the current contents of the satp +data structures pointed to by the current contents of the {\tt satp} register, and must only raise exceptions for implicit accesses that are generated as a result of instruction execution, not those that are performed speculatively. |