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| author | Andrew Waterman <andrew@sifive.com> | 2019-12-24 18:30:24 -0600 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-12-24 18:31:45 -0600 |
| commit | 7870844bc7ad7b64fc0f09a3f120f2175c48bfab (patch) | |
| tree | b2235c6e2c21b8d727e4a375a8956fd5accf74fe | |
| parent | d98903ed533561ac4d78dfb7748d6d4d6b1a6009 (diff) | |
| download | riscv-isa-manual-7870844bc7ad7b64fc0f09a3f120f2175c48bfab.zip riscv-isa-manual-7870844bc7ad7b64fc0f09a3f120f2175c48bfab.tar.gz riscv-isa-manual-7870844bc7ad7b64fc0f09a3f120f2175c48bfab.tar.bz2 | |
Clarify that access exceptions on jump targets are reported on the target
| -rw-r--r-- | src/rv32.tex | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index bbb2438..7c501f1 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -693,6 +693,10 @@ unconditional jumps and conditional branches. Control transfer instructions in RV32I do {\em not} have architecturally visible delay slots. +If an instruction access exception or instruction page fault occurs on the +target of a jump or taken branch, the exception is reported on the target +instruction, not on the jump or branch instruction. + \subsubsection*{Unconditional Jumps} \vspace{-0.1in} The jump and link (JAL) instruction uses the J-type |