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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-12 17:14:47 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-02-12 17:14:47 -0800 |
| commit | 0952756df48b7903e9fcf43efa4137ca0535cbb7 (patch) | |
| tree | 5493705cc889e1431513b74b9bbe14da02e15dc4 | |
| parent | c3d1f07012bd95eb5ecdf9b44e53ba84f87765d7 (diff) | |
| download | riscv-isa-manual-misa-ztso.zip riscv-isa-manual-misa-ztso.tar.gz riscv-isa-manual-misa-ztso.tar.bz2 | |
Repurpose misa.T to represent Ztsomisa-ztso
| -rw-r--r-- | src/machine.tex | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 57d9cc4..accf304 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -132,7 +132,7 @@ Bit & Character & Description \\ 16 & Q & Quad-precision floating-point extension \\ 17 & R & {\em Reserved} \\ 18 & S & Supervisor mode implemented \\ - 19 & T & {\em Tentatively reserved for Transactional Memory extension} \\ + 19 & T & Ztso extension \\ 20 & U & User mode implemented \\ 21 & V & {\em Tentatively reserved for Vector extension} \\ 22 & W & {\em Reserved} \\ @@ -165,6 +165,10 @@ The ``E'' bit is read-only. Unless {\tt misa} is hardwired to zero, the ``E'' bit always reads as the complement of the ``I'' bit. An implementation that supports both RV32E and RV32I can select RV32E by clearing the ``I'' bit. +The ``T'' bit is read-only, and all harts within the execution environment +must hardwire the ``T'' bit to the same value, indicating either that they +all implement RVWMO (0) or all implement RVTSO (1). + If an ISA feature {\em x} depends on an ISA feature {\em y}, then attempting to enable feature {\em x} but disable feature {\em y} results in both features being disabled. For example, setting ``F''=0 and ``D''=1 results in both |