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| author | Andrew Waterman <andrew@sifive.com> | 2021-09-08 17:15:22 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-09-08 17:15:22 -0700 |
| commit | 5e685a6f166cbcf6790491681e2d8ad5c3788d9a (patch) | |
| tree | 66958b128e00b3e5a9f4569280d8b740e77257a4 | |
| parent | 73bca53b4cf21f6ec39262e4472d4fa7a7e48551 (diff) | |
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FIOM may be hardwired when satp is hardwired
| -rw-r--r-- | src/machine.tex | 3 | ||||
| -rw-r--r-- | src/supervisor.tex | 2 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 3f921f5..11ca51c 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2357,7 +2357,8 @@ if an atomic instruction that accesses a region ordered as device I/O has its {\em aq} and/or {\em rl} bit set, then that instruction is ordered as though it accesses both device I/O and memory. -If S-mode is not supported, implementations may hardwire FIOM to zero. +If S-mode is not supported, or if {\tt satp}.MODE is hardwired to Bare, +the implementation may hardwire FIOM to zero. \begin{table}[h!] \begin{center} diff --git a/src/supervisor.tex b/src/supervisor.tex index 532fc72..08343be 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -845,6 +845,8 @@ if an atomic instruction that accesses a region ordered as device I/O has its {\em aq} and/or {\em rl} bit set, then that instruction is ordered as though it accesses both device I/O and memory. +If {\tt satp}.MODE is hardwired to Bare, the implementation may hardwire FIOM to zero. + \begin{table}[h!] \begin{center} \begin{tabular}{|c|l|} |