From 5e685a6f166cbcf6790491681e2d8ad5c3788d9a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 8 Sep 2021 17:15:22 -0700 Subject: FIOM may be hardwired when satp is hardwired --- src/machine.tex | 3 ++- src/supervisor.tex | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/machine.tex b/src/machine.tex index 3f921f5..11ca51c 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2357,7 +2357,8 @@ if an atomic instruction that accesses a region ordered as device I/O has its {\em aq} and/or {\em rl} bit set, then that instruction is ordered as though it accesses both device I/O and memory. -If S-mode is not supported, implementations may hardwire FIOM to zero. +If S-mode is not supported, or if {\tt satp}.MODE is hardwired to Bare, +the implementation may hardwire FIOM to zero. \begin{table}[h!] \begin{center} diff --git a/src/supervisor.tex b/src/supervisor.tex index 532fc72..08343be 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -845,6 +845,8 @@ if an atomic instruction that accesses a region ordered as device I/O has its {\em aq} and/or {\em rl} bit set, then that instruction is ordered as though it accesses both device I/O and memory. +If {\tt satp}.MODE is hardwired to Bare, the implementation may hardwire FIOM to zero. + \begin{table}[h!] \begin{center} \begin{tabular}{|c|l|} -- cgit v1.1