Merge branch 'counterinhibit-smt'

1 files changed, 8 insertions, 3 deletions

diff --git a/src/machine.tex b/src/machine.tex
index d723911..34c7046 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1685,6 +1685,10 @@ precision on all RV32 and RV64 systems.
 The counter registers have an arbitrary value after system reset, and
 can be written with a given value. Any CSR write takes effect after
 the writing instruction has otherwise completed.
+The {\tt mcycle} CSR may be shared between harts on the same core, in which
+case writes to {\tt mcycle} will be visible to those harts.
+The platform should provide a mechanism to indicate which harts share an {\tt
+mcycle} CSR.
 
 The hardware performance monitor includes 29 additional 64-bit event counters, {\tt
 mhpmcounter3}--{\tt mhpmcounter31}.  The event selector CSRs, {\tt
@@ -1895,6 +1899,10 @@ clear, the {\tt cycle}, {\tt instret}, or {\tt hpmcounter{\em n}} register
 increments as usual.  When the CY, IR, or HPM{\em n} bit is set, the
 corresponding counter does not increment.
 
+The {\tt mcycle} CSR may be shared between harts on the same core, in which
+case the {\tt mcountinhibit}.CY field is also shared between those harts,
+and so writes to {\tt mcountinhibit}.CY will be visible to those harts.
+
 If the {\tt mcountinhibit} register is not implemented, the implementation
 behaves as though the register were set to zero.
 
@@ -1904,9 +1912,6 @@ desirable to conditionally inhibit them to reduce energy consumption.
 Providing a single CSR to inhibit all counters also allows the counters to be
 atomically sampled.
 
-As all the harts on a processor core share a {\tt cycle} counter,
-so they share an {\tt mcountinhibit}.CY bit.
-
 Because the {\tt time} counter can be shared between multiple cores, it
 cannot be inhibited with the {\tt mcountinhibit} mechanism.
 \end{commentary}