From 4eeaf69b4afcb711be566f98cbe19425c6a6cc49 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Tue, 25 Jun 2019 00:07:46 -0700 Subject: Indicate that mcycle can be shared between harts When reading through the manual for the QEMU patches to implement mcounterinhibit I found that the commentary allows mcycle to be shared between harts. I actually really don't like this behavior, but I can understand that it may make sense for some systems. Regardless, the normative text of the ISA manual should match the commentary. This patch introduces the concept that modifications of a CSR on one hart may cause the value on other harts to change. If I understand correctly that's not quite a WARL field, which can only change upon writes. I don't think it's worth giving this a name, though, as hopefull it'll only apply to mcycle. Signed-off-by: Palmer Dabbelt --- src/machine.tex | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/machine.tex b/src/machine.tex index 302a620..9bbb48b 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1698,7 +1698,9 @@ precision on all RV32 and RV64 systems. The counter registers have an arbitrary value after system reset, and can be written with a given value. Any CSR write takes effect after -the writing instruction has otherwise completed. +the writing instruction has otherwise completed. Writes to {\tt mcycle} on one +hart may change the value of {\tt mcycle} on other harts, the platform must +provide a mechanism to indicate when this behavior will occur. The hardware performance monitor includes 29 additional 64-bit event counters, {\tt mhpmcounter3}--{\tt mhpmcounter31}. The event selector CSRs, {\tt @@ -1907,7 +1909,9 @@ their accessibility is not affected by the setting of this register. When the CY, IR, or HPM{\em n} bit in the {\tt mcountinhibit} register is clear, the {\tt cycle}, {\tt instret}, or {\tt hpmcounter{\em n}} register increments as usual. When the CY, IR, or HPM{\em n} bit is set, the -corresponding counter does not increment. +corresponding counter does not increment. Writes to {\tt mcountinhibit}.CY may +change the value of {\tt mcountintihib}.CY on other harts, the platform must +provide a mechanism to indicate when this behavior will occur. If the {\tt mcountinhibit} register is not implemented, the implementation behaves as though the register were set to zero. -- cgit v1.1 From d725d8af2dfc8c637873a19e91ec4df747460eea Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Tue, 25 Jun 2019 00:19:02 -0700 Subject: Don't mandate that multiple harts on a core share mcycle The commentary indicates that sharing mcycle between harts is mandatory, but I don't think that's a good idea -- both because it's introducing a constraint that is very hard to formalize (ie, WTF is a core) and because I think some systems will desire different behavior. This patch softens the wording in the commentary to avoid the appearance that sharing mcycle between threads is mandatory. Signed-off-by: Palmer Dabbelt --- src/machine.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine.tex b/src/machine.tex index 9bbb48b..9416df9 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1922,7 +1922,7 @@ desirable to conditionally inhibit them to reduce energy consumption. Providing a single CSR to inhibit all counters also allows the counters to be atomically sampled. -As all the harts on a processor core share a {\tt cycle} counter, +As all the harts on a processor core may share a {\tt cycle} counter, so they share an {\tt mcountinhibit}.CY bit. Because the {\tt time} counter can be shared between multiple cores, it -- cgit v1.1 From 50822297ef9ce9bf35d1853453804aaea7609df8 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 25 Jun 2019 17:10:10 -0700 Subject: Touch up the mcycle text --- src/machine.tex | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/machine.tex b/src/machine.tex index cde159e..34c7046 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1684,9 +1684,11 @@ precision on all RV32 and RV64 systems. The counter registers have an arbitrary value after system reset, and can be written with a given value. Any CSR write takes effect after -the writing instruction has otherwise completed. Writes to {\tt mcycle} on one -hart may change the value of {\tt mcycle} on other harts, the platform must -provide a mechanism to indicate when this behavior will occur. +the writing instruction has otherwise completed. +The {\tt mcycle} CSR may be shared between harts on the same core, in which +case writes to {\tt mcycle} will be visible to those harts. +The platform should provide a mechanism to indicate which harts share an {\tt +mcycle} CSR. The hardware performance monitor includes 29 additional 64-bit event counters, {\tt mhpmcounter3}--{\tt mhpmcounter31}. The event selector CSRs, {\tt @@ -1895,9 +1897,11 @@ their accessibility is not affected by the setting of this register. When the CY, IR, or HPM{\em n} bit in the {\tt mcountinhibit} register is clear, the {\tt cycle}, {\tt instret}, or {\tt hpmcounter{\em n}} register increments as usual. When the CY, IR, or HPM{\em n} bit is set, the -corresponding counter does not increment. Writes to {\tt mcountinhibit}.CY may -change the value of {\tt mcountintihib}.CY on other harts, the platform must -provide a mechanism to indicate when this behavior will occur. +corresponding counter does not increment. + +The {\tt mcycle} CSR may be shared between harts on the same core, in which +case the {\tt mcountinhibit}.CY field is also shared between those harts, +and so writes to {\tt mcountinhibit}.CY will be visible to those harts. If the {\tt mcountinhibit} register is not implemented, the implementation behaves as though the register were set to zero. @@ -1908,9 +1912,6 @@ desirable to conditionally inhibit them to reduce energy consumption. Providing a single CSR to inhibit all counters also allows the counters to be atomically sampled. -As all the harts on a processor core may share a {\tt cycle} counter, -so they share an {\tt mcountinhibit}.CY bit. - Because the {\tt time} counter can be shared between multiple cores, it cannot be inhibited with the {\tt mcountinhibit} mechanism. \end{commentary} -- cgit v1.1