riscv-isa-manual.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-08-15	hypervisor: add performance counter delta registersbonzini-hpmdelta	Paolo Bonzini	2	-0/+52
2019-07-30	Use consistent terms for exception types	Andrew Waterman	4	-28/+28
2019-07-26	Add @marceg to contributors	Andrew Waterman	1	-2/+3
2019-07-26	The execution environment must guarantee harts make progress	Andrew Waterman	1	-0/+17
2019-07-23	Fix extension ordering in naming chapter and preface	Andrew Waterman	2	-6/+7
2019-07-21	Move N extension into its own chapter in the priv spec	Andrew Waterman	9	-371/+356
2019-07-18	More hypervisor updates courtesy of @jhauser-us	Andrew Waterman	1	-91/+282
2019-07-18	Fix poor figure placement	Andrew Waterman	1	-2/+3
2019-07-12	Update SweRV project URL (#408)	Thomas Wicki	1	-1/+1
2019-07-12	Improve description of mtimecmp code sequence	Andrew Waterman	1	-1/+3
2019-07-12	Clarify that mtime writes/ticks can also clear MTIP	Andrew Waterman	1	-2/+3
2019-07-09	Clarify that mtvec is WARL (#406)	Alex Bradbury	1	-1/+1
2019-06-26	Clarify which hints are C.NOP hints and which are C.ADDI hints	Andrew Waterman	1	-4/+5
2019-06-25	Merge branch 'counterinhibit-smt'	Andrew Waterman	1	-3/+8
2019-06-25	Touch up the mcycle text	Andrew Waterman	1	-9/+10
2019-06-25	Merge branch 'master' into counterinhibit-smt	Andrew Waterman	5	-42/+26
2019-06-25	ECALL and EBREAK don't retire	Andrew Waterman	1	-0/+2
2019-06-25	Don't mandate that multiple harts on a core share mcycle	Palmer Dabbelt	1	-1/+1
2019-06-25	Indicate that mcycle can be shared between harts	Palmer Dabbelt	1	-2/+6
2019-06-24	MPRV affects endianness	Andrew Waterman	2	-6/+7
2019-06-24	Remove endianness dependence on PTE.U	Andrew Waterman	2	-33/+9
2019-06-24	Fix spelling	Andrew Waterman	1	-2/+2
2019-06-24	Update contributors	Andrew Waterman	1	-1/+1
2019-06-24	Clarify that, if all PMPs are OFF, all S/U accesses fail	Andrew Waterman	1	-0/+5
2019-06-21	Merge pull request #397 from riscv/endianness	Andrew Waterman	5	-15/+90
2019-06-21	Clarify PC behavior when XLEN < max supported XLEN	Andrew Waterman	1	-0/+2
2019-06-21	State endianness assumption of code example	Andrew Waterman	1	-2/+3
2019-06-21	Clarify sign of REM; add commentary	Andrew Waterman	2	-2/+10
2019-06-21	Changes to unprivileged spec for bi[g]-endian support	Andrew Waterman	4	-13/+38
2019-06-21	Bump version of unprivileged spec to 20190621-draft	Andrew Waterman	2	-2/+52
2019-06-21	Fix bad RV32I chapter formatting	Andrew Waterman	1	-48/+48
2019-06-21	Clarify SBE/SFENCE interaction	Andrew Waterman	1	-1/+12
2019-06-21	Update contributors	Andrew Waterman	1	-1/+2
2019-06-21	add BlackParrot and BaseJump Manycore (#396)	black-parrot	1	-0/+2
2019-06-21	Fix preface style	Andrew Waterman	1	-2/+2
2019-06-21	Merge pull request #395 from riscv/endianness	Andrew Waterman	4	-38/+215
2019-06-21	Add mstatush to preface	Andrew Waterman	1	-0/+2
2019-06-21	Need SFENCE after change to SBE	Andrew Waterman	1	-0/+3
2019-06-21	Spelling	Andrew Waterman	2	-2/+2
2019-06-21	Bi-endian systems reset as little-endian	Andrew Waterman	1	-0/+2
2019-06-21	Add commentary	Andrew Waterman	1	-0/+9
2019-06-19	Add endianness control proposal to priv spec	Andrew Waterman	4	-37/+198
2019-06-16	Bump priv spec to v1.12-draft	Andrew Waterman	2	-6/+40
2019-06-16	Hypervisor v0.4 draft	Andrew Waterman	3	-314/+379
2019-06-08	Added text to indicate this is the ratified 1.11 version of the spec.Ratified-IMFDQC-and-Priv-v1.11	Krste Asanovic	2	-6/+7
2019-06-08	Updated preface to indicate this is now ratified spec.	Krste Asanovic	2	-19/+19
2019-05-31	Merge pull request #391 from imphil/counter-enable-typo	Krste Asanovic	1	-1/+1
2019-05-31	Tiny editorial fix	Philipp Wagner	1	-1/+1
2019-05-21	Adding FENCE to the table of RV64 HINT instructions (#387)	Luís Marques	1	-1/+2
2019-05-15	Correct iteration in LR/SC CAS example. (#384)	David-Horner	1	-2/+3