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| author | Andrew Waterman <andrew@sifive.com> | 2017-07-30 23:58:12 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-07-30 23:58:12 -0700 |
| commit | 4809ae416c8267d9a54c701439364349d72a98df (patch) | |
| tree | 9645010a03cedcb94f93e060fa9be732458ffdbe | |
| parent | 54afbb9d65eb2cb17e5b49365a476fb656d153ba (diff) | |
| download | riscv-isa-manual-4809ae416c8267d9a54c701439364349d72a98df.zip riscv-isa-manual-4809ae416c8267d9a54c701439364349d72a98df.tar.gz riscv-isa-manual-4809ae416c8267d9a54c701439364349d72a98df.tar.bz2 | |
clarify that more-privileged interrupts are of higher priority
| -rw-r--r-- | src/machine.tex | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/machine.tex b/src/machine.tex index 22f8176..b4e847b 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1313,10 +1313,12 @@ delegated privilege mode (S or U) and that mode's interrupt enable bit (SIE or UIE in {\tt mstatus}) is set, or if the current privilege mode is less than the delegated privilege mode. -Multiple simultaneous interrupts and traps at the same privilege level -are handled in the following decreasing priority order: external -interrupts, software interrupts, timer interrupts, then finally any -synchronous traps. +Multiple simultaneous interrupts destined for different privilege modes are +handled in decreasing order of destined privilege mode. Multiple simultaneous +interrupts destined for the same privilege mode are handled in the following +decreasing priority order: external interrupts, software interrupts, then +timer interrupts. Synchronous exceptions are of lower priority than all +interrupts. \subsection{Machine Timer Registers ({\tt mtime} and {\tt mtimecmp})} |