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| author | Andrew Waterman <andrew@sifive.com> | 2019-12-02 09:56:44 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-02 09:56:44 -0800 |
| commit | 99eb76ac3c19eb3ebc6c2f91c4bfb85baf187cd0 (patch) | |
| tree | 31063f2e63e195f253a4fefe40a9e6ae3ab26f7f | |
| parent | 6d33722fe1c2f07c2c43feef04c17ad856d9b277 (diff) | |
| parent | 3efbb03df8b7490cf3975b59e8f67966cac43168 (diff) | |
| download | env-99eb76ac3c19eb3ebc6c2f91c4bfb85baf187cd0.zip env-99eb76ac3c19eb3ebc6c2f91c4bfb85baf187cd0.tar.gz env-99eb76ac3c19eb3ebc6c2f91c4bfb85baf187cd0.tar.bz2 | |
Merge pull request #15 from chihminchao/ecall_and_vector
Ecall and vector
| -rw-r--r-- | encoding.h | 2 | ||||
| -rw-r--r-- | p/riscv_test.h | 20 |
2 files changed, 22 insertions, 0 deletions
@@ -22,6 +22,7 @@ #define MSTATUS_TVM 0x00100000 #define MSTATUS_TW 0x00200000 #define MSTATUS_TSR 0x00400000 +#define MSTATUS_VS 0x01800000 #define MSTATUS32_SD 0x80000000 #define MSTATUS_UXL 0x0000000300000000 #define MSTATUS_SXL 0x0000000C00000000 @@ -36,6 +37,7 @@ #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 #define SSTATUS_MXR 0x00080000 +#define SSTATUS_VS 0x01800000 #define SSTATUS32_SD 0x80000000 #define SSTATUS_UXL 0x0000000300000000 #define SSTATUS64_SD 0x8000000000000000 diff --git a/p/riscv_test.h b/p/riscv_test.h index 7cb00d5..bb7ced6 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -18,6 +18,11 @@ RVTEST_FP_ENABLE; \ .endm +#define RVTEST_RV64UV \ + .macro init; \ + RVTEST_VECTOR_ENABLE; \ + .endm + #define RVTEST_RV32U \ .macro init; \ .endm @@ -27,6 +32,11 @@ RVTEST_FP_ENABLE; \ .endm +#define RVTEST_RV32UV \ + .macro init; \ + RVTEST_VECTOR_ENABLE; \ + .endm + #define RVTEST_RV64M \ .macro init; \ RVTEST_ENABLE_MACHINE; \ @@ -95,6 +105,12 @@ csrs mstatus, a0; \ csrwi fcsr, 0 +#define RVTEST_VECTOR_ENABLE \ + li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \ + (MSTATUS_FS & (MSTATUS_FS >> 1)); \ + csrs mstatus, a0; \ + csrwi fcsr, 0 + #define RISCV_MULTICORE_DISABLE \ csrr a0, mhartid; \ 1: bnez a0, 1b @@ -187,6 +203,8 @@ reset_vector: \ #define RVTEST_PASS \ fence; \ li TESTNUM, 1; \ + li a7, 93; \ + li a0, 0; \ ecall #define TESTNUM gp @@ -195,6 +213,8 @@ reset_vector: \ 1: beqz TESTNUM, 1b; \ sll TESTNUM, TESTNUM, 1; \ or TESTNUM, TESTNUM, 1; \ + li a7, 93; \ + addi a0, TESTNUM, 0; \ ecall //----------------------------------------------------------------------- |