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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-27 23:44:26 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-28 00:01:42 -0800 |
| commit | 3efbb03df8b7490cf3975b59e8f67966cac43168 (patch) | |
| tree | 31063f2e63e195f253a4fefe40a9e6ae3ab26f7f | |
| parent | ee995655e60f5ca4bc4b3d62fec7a82c066cf811 (diff) | |
| download | env-3efbb03df8b7490cf3975b59e8f67966cac43168.zip env-3efbb03df8b7490cf3975b59e8f67966cac43168.tar.gz env-3efbb03df8b7490cf3975b59e8f67966cac43168.tar.bz2 | |
rvv: add mstatus.vs definition and initial mcaro
1. mstatus.vs is similar to mstatus.fs but desiged for vector extension.
2. add mstatus.vs initialization macro. The macro also enables floating unit.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | encoding.h | 2 | ||||
| -rw-r--r-- | p/riscv_test.h | 16 |
2 files changed, 18 insertions, 0 deletions
@@ -22,6 +22,7 @@ #define MSTATUS_TVM 0x00100000 #define MSTATUS_TW 0x00200000 #define MSTATUS_TSR 0x00400000 +#define MSTATUS_VS 0x01800000 #define MSTATUS32_SD 0x80000000 #define MSTATUS_UXL 0x0000000300000000 #define MSTATUS_SXL 0x0000000C00000000 @@ -36,6 +37,7 @@ #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 #define SSTATUS_MXR 0x00080000 +#define SSTATUS_VS 0x01800000 #define SSTATUS32_SD 0x80000000 #define SSTATUS_UXL 0x0000000300000000 #define SSTATUS64_SD 0x8000000000000000 diff --git a/p/riscv_test.h b/p/riscv_test.h index edeb34f..bb7ced6 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -18,6 +18,11 @@ RVTEST_FP_ENABLE; \ .endm +#define RVTEST_RV64UV \ + .macro init; \ + RVTEST_VECTOR_ENABLE; \ + .endm + #define RVTEST_RV32U \ .macro init; \ .endm @@ -27,6 +32,11 @@ RVTEST_FP_ENABLE; \ .endm +#define RVTEST_RV32UV \ + .macro init; \ + RVTEST_VECTOR_ENABLE; \ + .endm + #define RVTEST_RV64M \ .macro init; \ RVTEST_ENABLE_MACHINE; \ @@ -95,6 +105,12 @@ csrs mstatus, a0; \ csrwi fcsr, 0 +#define RVTEST_VECTOR_ENABLE \ + li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \ + (MSTATUS_FS & (MSTATUS_FS >> 1)); \ + csrs mstatus, a0; \ + csrwi fcsr, 0 + #define RISCV_MULTICORE_DISABLE \ csrr a0, mhartid; \ 1: bnez a0, 1b |