aboutsummaryrefslogtreecommitdiff
path: root/debug/targets/SiFive/HiFiveUnleashed.py
blob: 04f6cef09a3c7e9eb3e83d993045beb200c969bf (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
import targets

class E51(targets.Hart):
    xlen = 64
    ram = 0x80000000
    ram_size = 1024 * 1024
    bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
    instruction_hardware_breakpoint_count = 2
    reset_vectors = [0x1004]
    misa = 0x8000000000101105

class U54(targets.Hart):
    xlen = 64
    ram = 0x80000000
    ram_size = 1024 * 1024
    bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
    instruction_hardware_breakpoint_count = 2
    reset_vectors = [0x1004]
    misa = 0x800000000014112d

class HiFiveUnleashed(targets.Target):
    support_hasel = False
    support_memory_sampling = False # Needs SBA
    harts = [E51(), U54(), U54(), U54(), U54()]