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| author | Tim Newsome <tim@sifive.com> | 2020-12-31 12:48:19 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2020-12-31 12:48:19 -0800 |
| commit | 7d069666a5841e5e5b3ba1723c6af26925a35a9c (patch) | |
| tree | c4c87bce99b8f2ce58a74e7250dbb1eeb778d78f /debug/targets/SiFive/HiFiveUnleashed.py | |
| parent | 3496243928e3dbd562dd84bcf9e6222221d423e5 (diff) | |
| download | riscv-tests-7d069666a5841e5e5b3ba1723c6af26925a35a9c.zip riscv-tests-7d069666a5841e5e5b3ba1723c6af26925a35a9c.tar.gz riscv-tests-7d069666a5841e5e5b3ba1723c6af26925a35a9c.tar.bz2 | |
Make HiFiveUnleashed tests clean.
HiFiveUnleashed-flash fails som address translation tests. Possibly that
would be fixed when https://github.com/riscv/riscv-tests/pull/313
merges.
Diffstat (limited to 'debug/targets/SiFive/HiFiveUnleashed.py')
| -rw-r--r-- | debug/targets/SiFive/HiFiveUnleashed.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/debug/targets/SiFive/HiFiveUnleashed.py b/debug/targets/SiFive/HiFiveUnleashed.py index 9bf7cae..04f6cef 100644 --- a/debug/targets/SiFive/HiFiveUnleashed.py +++ b/debug/targets/SiFive/HiFiveUnleashed.py @@ -4,6 +4,7 @@ class E51(targets.Hart): xlen = 64 ram = 0x80000000 ram_size = 1024 * 1024 + bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1 instruction_hardware_breakpoint_count = 2 reset_vectors = [0x1004] misa = 0x8000000000101105 @@ -12,10 +13,12 @@ class U54(targets.Hart): xlen = 64 ram = 0x80000000 ram_size = 1024 * 1024 + bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1 instruction_hardware_breakpoint_count = 2 reset_vectors = [0x1004] misa = 0x800000000014112d class HiFiveUnleashed(targets.Target): support_hasel = False + support_memory_sampling = False # Needs SBA harts = [E51(), U54(), U54(), U54(), U54()] |