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* Another pylint upgrade.
Lots of format string changes, which are more readable.
More files to come...
* Satisfy pylint for two more files.
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regions (#388)
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It includes the name in quotes:
```* 2 Thread 1 "Current Execution" (Name: Current Execution) 0x10000100 in main```
Just ignore that part.
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This feature lets you easily interact with the gdb after the test has
run to a certain point.
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Disconnects from gdb, and then reconnects, making sure that didn't
change any of the registers.
This test will start passing when
https://github.com/riscv/riscv-openocd/pull/661 merges.
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It's not an argument to spike anymore.
Also switch testing the vector unit from multi-gdb to `-rtos hwthread`.
This exposes a bug in OpenOCD (which is already fixed).
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1. Don't run all tests in multi-spike. Extra coverage is negligible, and
it just takes too long.
2. Increase a few timeouts.
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* Test debugging multiple spikes in a daisy chain.
* Hugely speed up rbb_daisychain.
Now 2 dual-hart spikes are less than 4x slower than a single dual-hart
spike.
* WIP
* Test daisy chained homogeneous spike instances.
For OpenOCD, this means we're checking that we can talk to multiple
TAPs. Next up is heterogeneous testing.
* Enable Sv48Test.
Didn't mean to disable it with this commit.
* Test authentication again.
Another change I hadn't meant to push...
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* Add FreeRTOS smoke tests.
Make sure that OpenOCD can access all threads in a FreeRTOS binary on
single-hart RV32 and RV64.
* Also test `-rtos FreeRTOS`.
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* WIP
* WIP
* Vector test seems to work well with spike.
* Check a0 in case the program didn't work right.
* Return not applicable if compile doesn't support V
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Also use sys.exit instead of exit, per new pylint's suggestion.
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* Improve address translation tests.
Check that the mode we're testing is supported by hardware before
running the test.
Test with high address bits set, which catches a bug in OpenOCD.
* Turn off PMP for address translation test.
Otherwise it doesn't pass on HiFive Unleashed.
* Run TranslateTest on random hart.
Once https://github.com/riscv/riscv-openocd/pull/459 merges that will work.
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Otherwise it only passes intermittently when I change _start, which is
very confusing.
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This was changed by https://github.com/riscv/riscv-isa-sim/pull/417
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Also fix bug in parsing nan.
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* WIP
* Add vector register smoketest.
Also redo the gdb value parsing code to accommodate the more complicated
way that vector registers look.
* Test vector access a little more thoroughly.
* Revert unnecessary changes.
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If it's in the path, at least. This way you get human readable assembly
in the log instead of hex values.
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This catches more corner cases where this may be a problem.
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* Improve parallellism in debug test Makefile
Now each test is an individual make target, so you can get the most out
of however many cores you have. On my 12-core system, `make` went from
2m45s to 42s, and `make all` went from `3m25s` to `2m39s`.
If you have few cores, this change may actually slow things down a bit,
because ExamineTarget is run for every gdbserver.py invocation.
* Remove test target.
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The impetus for this was mostly that after my Ubuntu upgrade, pylint
suddenly starting to apply python3 rules, and I suppose it's time to
adopt python 3 now that it's been released for more than a decade.
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* Parse inf/nan floats.
* Enable mstatus.fs in SimpleF18Test
Also accept "unable to fetch" message when FPRs aren't supported.
* Add config files for HiFive Unleashed.
* Add configs to flash HiFive Unleashed.
All tests pass.
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Instead of relying on $RISCV. Using $RISCV was common in the early
days, but nowadays many tools are simply installed alongside the rest of
the system.
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* Let the debugger enable mstatus.F if necessary.
* Ignore (some) gdb debug output.
* Increase timeout.
* Make newer version of pylint happy.
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* Parse floats the way mainline gdb prints them.
For 64-bit floats, it shows both float and double results. Now more
tests pass using mainline gdb.
* Disable ANSI when talking to gdb.
Helps more tests pass with mainline gdb.
* Parse {float=...,double=...} in "info registers"
Makes tests work better with mainline gdb.
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Also work with the new command line options that were renamed in
https://github.com/riscv/riscv-isa-sim/pull/299
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Passes on spike and Arty. Won't merge until
https://github.com/riscv/riscv-openocd/pull/364 merges.
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This test confirms that in SMP configurations OpenOCD halts the harts
near-simulatenously. (It'll also check for resume, but that's not
implemented yet so commented out for now.)
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* WIP
* Use hwthread everywhere.
* Test `-rtos hwthread`.
Also tweak timeouts a bit so that we don't have ridiculous timeouts for
simple operations.
* Tweak timeouts so tests pass on a loaded system.
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Increase some timeouts in case memory access is slow.
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TriggerDmode, ProgramHwWatchpoint, ProgramSwWatchpoint.
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Not all tests pass when run out of flash yet, but it's getting a lot
closer. The ones still failing on HiFive1-flash are: DebugSymbols,
Hwbp2, InstantHaltTest, TriggerDmode, TriggerLoadAddressInstant, and
TriggerStoreAddressInstant.
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Also tiny cleanups, making pylint happy.
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gdb in riscv-tools doesn't automatically create a "custom" group like
mainline gdb does.
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Only works against spike, where I've implemented some custom debug
registers to test against.
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This allows me to see the final valgrind output on OpenOCD, so I can
watch for memory leaks when using --server_cmd "valgrind
--leak-check=full openocd".
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The test actually wasn't checking interrupt counts at all. Fixing it
required some other changes:
Make sure all harts get to run
Add some retries, since on a loaded machine against spike both harts
might not get to run, even if you give spike a generous amount of time
to do so.
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