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authorTim Newsome <tim@sifive.com>2019-04-04 11:40:08 -0700
committerGitHub <noreply@github.com>2019-04-04 11:40:08 -0700
commit74aecdcce266d2d7f73df415cb83b6e7816e0dc5 (patch)
treed712af2e9f68d10fafbcaf64176f5aae7411e622 /debug/testlib.py
parent91b6f8fdda47323fd6af16320b6560d325ac6317 (diff)
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Test simultaneous resume using hasel. (#186)
Passes on spike and Arty. Won't merge until https://github.com/riscv/riscv-openocd/pull/364 merges.
Diffstat (limited to 'debug/testlib.py')
-rw-r--r--debug/testlib.py7
1 files changed, 6 insertions, 1 deletions
diff --git a/debug/testlib.py b/debug/testlib.py
index c4b785c..b3163c3 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -58,7 +58,8 @@ def compile(args, xlen=32): # pylint: disable=redefined-builtin
class Spike(object):
# pylint: disable=too-many-instance-attributes
def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
- isa=None, progbufsize=None, dmi_rti=None, abstract_rti=None):
+ isa=None, progbufsize=None, dmi_rti=None, abstract_rti=None,
+ support_hasel=True):
"""Launch spike. Return tuple of its process and the port it's running
on."""
self.process = None
@@ -66,6 +67,7 @@ class Spike(object):
self.progbufsize = progbufsize
self.dmi_rti = dmi_rti
self.abstract_rti = abstract_rti
+ self.support_hasel = support_hasel
if target.harts:
harts = target.harts
@@ -133,6 +135,9 @@ class Spike(object):
if not self.abstract_rti is None:
cmd += ["--abstract-rti", str(self.abstract_rti)]
+ if not self.support_hasel:
+ cmd.append("--without-hasel")
+
assert len(set(t.ram for t in harts)) == 1, \
"All spike harts must have the same RAM layout"
assert len(set(t.ram_size for t in harts)) == 1, \