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| author | Tim Newsome <tim@sifive.com> | 2018-08-27 13:17:51 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-08-29 15:00:23 -0700 |
| commit | 4dddbc79ada7f0a836cf538676c57c8df103ccf6 (patch) | |
| tree | 7c22387fa778244eef8ff1d30a55ffb005b09fea /debug/testlib.py | |
| parent | 40dbc5118c9ac4beb4fc0a28cf4ad4cb56536111 (diff) | |
| download | riscv-tests-4dddbc79ada7f0a836cf538676c57c8df103ccf6.zip riscv-tests-4dddbc79ada7f0a836cf538676c57c8df103ccf6.tar.gz riscv-tests-4dddbc79ada7f0a836cf538676c57c8df103ccf6.tar.bz2 | |
Add test case for `riscv expose_custom`.
Only works against spike, where I've implemented some custom debug
registers to test against.
Diffstat (limited to 'debug/testlib.py')
| -rw-r--r-- | debug/testlib.py | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/debug/testlib.py b/debug/testlib.py index 1d46b6c..6adc43a 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -552,6 +552,18 @@ class Gdb(object): value = shlex.split(output.split('=')[-1].strip())[1] return value + def info_registers(self, group): + output = self.command("info registers %s" % group) + result = {} + for line in output.splitlines(): + if "Could not fetch" in line: + name, value = line.split(None, 1) + else: + name, hex_value, _ = line.split(None, 2) + value = int(hex_value, 0) + result[name] = value + return result + def stepi(self): output = self.command("stepi", ops=10) return output |