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Age	Commit message (Collapse)	Author	Files	Lines
2024-05-01	[debug tests] increase remotetimeout for all spike-based targets (#553)	Anatoly Parshintsev	1	-1/+1
	Spike simulator is very demanding to CPU resources. This causes debug tests to sporadically fail on slower machines. Increasing of gdb's `remotetimeout` should get rid of such failures, unless we run the testsuite on a potato. The only downside is that if OpenOCD is broken, tests can run longer. However, I think this is the sacrifice we can make, since execution time is not affected if everything works as expected.
2023-07-17	debug: Add support_unavailable_control property.	Tim Newsome	1	-0/+1

2022-10-21	Change memory address used in debug tests. (#422)	Tim Newsome	1	-1/+1
	https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART at the address we were using in our 32-bit debug tests.
2021-05-20	Test multiple heterogeneous spike instances. (#338)	Tim Newsome	1	-4/+0

2021-05-07	Test daisy chained homogeneous spike instances. (#334)	Tim Newsome	1	-1/+2
	* Test debugging multiple spikes in a daisy chain. * Hugely speed up rbb_daisychain. Now 2 dual-hart spikes are less than 4x slower than a single dual-hart spike. * WIP * Test daisy chained homogeneous spike instances. For OpenOCD, this means we're checking that we can talk to multiple TAPs. Next up is heterogeneous testing. * Enable Sv48Test. Didn't mean to disable it with this commit. * Test authentication again. Another change I hadn't meant to push...
2021-04-13	Add FreeRTOS smoke tests. (#333)	Tim Newsome	1	-1/+2
	* Add FreeRTOS smoke tests. Make sure that OpenOCD can access all threads in a FreeRTOS binary on single-hart RV32 and RV64. * Also test `-rtos FreeRTOS`.
2020-12-31	Make HiFiveUnleashed tests clean.	Tim Newsome	1	-0/+1
	HiFiveUnleashed-flash fails som address translation tests. Possibly that would be fixed when https://github.com/riscv/riscv-tests/pull/313 merges.
2020-12-14	Add tests for memory sampling feature. (#300)	Tim Newsome	1	-0/+1

2020-02-14	Add tests for vector register access (#244)	Tim Newsome	1	-3/+5
	* WIP * Add vector register smoketest. Also redo the gdb value parsing code to accommodate the more complicated way that vector registers look. * Test vector access a little more thoroughly. * Revert unnecessary changes.
2019-12-18	Hardcode misa values for all spike targets. (#227)	Tim Newsome	1	-1/+4
	`make` now takes 31s, `make all` takes 1m53s. The new CheckMisa test ensures that the misa value specified in the configuration is correct.
2019-05-16	Cover with/without halt groups. (#191)	Tim Newsome	1	-1/+1
	Also work with the new command line options that were renamed in https://github.com/riscv/riscv-isa-sim/pull/299
2019-04-08	Test lack of abstract CSR access. (#187)	Tim Newsome	1	-1/+2

2018-12-31	Add testing of run-test/idle cases.	Tim Newsome	1	-1/+1

2018-08-29	Add test case for `riscv expose_custom`.	Tim Newsome	1	-0/+1
	Only works against spike, where I've implemented some custom debug registers to test against.
2017-12-27	Test FPRs that aren't XLEN in size.	Tim Newsome	1	-1/+2
	Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
2017-09-29	Fix tests to work in multi-gdb mode.	Tim Newsome	1	-1/+1
	The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them.
2017-09-19	Allow multiple reset vectors.	Tim Newsome	1	-1/+1
	Some boards have jumpers that control the reset vector, and forcing them one way or another is more annoying than dealing with it in software.
2017-09-01	Use 32-bit link script for 32-bit target.	Tim Newsome	1	-1/+1

2017-08-28	Increase remotetimeout for spike targets.	Tim Newsome	1	-0/+1
	On overloaded systems, when executing compare-sections, otherwise gdb might hit a timeout and the compare-sections code doesn't deal with it. (You get an error message complaining that 130 is not a valid hex digit.)
2017-08-28	Make the debug tests aware of multicore.	Tim Newsome	1	-1/+6
	Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-06-26	Move target definition into individual files.	Tim Newsome	1	-0/+12
	Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.