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| author | Tim Newsome <tim@sifive.com> | 2023-06-23 17:06:31 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2023-07-17 09:34:55 -0700 |
| commit | a29522f3e4baec1a50beb01ec70d69a94ac0083c (patch) | |
| tree | e75cd638c0fd87fb549444adcba8ca1cf09fd249 /debug/targets/RISC-V/spike32.py | |
| parent | 65e27a9d3851c35687b1d02793b452f598d1f7ae (diff) | |
| download | riscv-tests-a29522f3e4baec1a50beb01ec70d69a94ac0083c.zip riscv-tests-a29522f3e4baec1a50beb01ec70d69a94ac0083c.tar.gz riscv-tests-a29522f3e4baec1a50beb01ec70d69a94ac0083c.tar.bz2 | |
debug: Add support_unavailable_control property.
Diffstat (limited to 'debug/targets/RISC-V/spike32.py')
| -rw-r--r-- | debug/targets/RISC-V/spike32.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index 0d67ebd..f0afd88 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -17,6 +17,7 @@ class spike32(targets.Target): implements_custom_test = True support_memory_sampling = False # Needs SBA freertos_binary = "bin/RTOSDemo32.axf" + support_unavailable_control = True def create(self): # 64-bit FPRs on 32-bit target |