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| author | Tim Newsome <tim@sifive.com> | 2022-10-21 09:23:36 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-10-21 09:23:36 -0700 |
| commit | 7e77eedc514a6538e07b666c36449e54080054b7 (patch) | |
| tree | 69bc3364de7a87659287db016c3b9ac8787f551b /debug/targets/RISC-V/spike32.py | |
| parent | 1d03f2a827f2a37f7d7b65218ef679fbafc797da (diff) | |
| download | riscv-tests-7e77eedc514a6538e07b666c36449e54080054b7.zip riscv-tests-7e77eedc514a6538e07b666c36449e54080054b7.tar.gz riscv-tests-7e77eedc514a6538e07b666c36449e54080054b7.tar.bz2 | |
Change memory address used in debug tests. (#422)
https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART
at the address we were using in our 32-bit debug tests.
Diffstat (limited to 'debug/targets/RISC-V/spike32.py')
| -rw-r--r-- | debug/targets/RISC-V/spike32.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index 17d28fb..0d67ebd 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -3,7 +3,7 @@ import testlib class spike32_hart(targets.Hart): xlen = 32 - ram = 0x10000000 + ram = 0x10100000 ram_size = 0x10000000 bad_address = ram - 8 instruction_hardware_breakpoint_count = 4 |