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riscv-tools/riscv-tests.git
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cs152-sp18-lab3
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debug-clear-satp
debug-delete-sim
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Age
Commit message (
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Author
Files
Lines
2016-09-29
Update dmode test to match spec.
Tim Newsome
1
-33
/
+53
2016-09-29
Clear triggers during entry.
Tim Newsome
1
-0
/
+9
2016-09-02
Fix/add to instant trigger tests.
Tim Newsome
1
-1
/
+3
2016-09-01
Add some immediate trigger tests.
Tim Newsome
1
-6
/
+6
2016-09-01
Create TriggerTest.
Tim Newsome
1
-0
/
+97
2016-08-16
Simplify test_function_call.
Tim Newsome
1
-0
/
+18
2016-07-28
Add tests for virtual priv register.
Tim Newsome
1
-0
/
+11
2016-07-19
Add 32-bit support.
Tim Newsome
1
-1
/
+9
2016-07-19
I think I've finally got malloc working right.
Tim Newsome
2
-5
/
+8
2016-07-19
Make variables local again, now that gdb is "fixed."
Tim Newsome
1
-6
/
+2
2016-07-19
Add test for gdb function calls.
Tim Newsome
2
-0
/
+602
2016-07-18
Test step over invalid instruction.
Tim Newsome
1
-7
/
+14
2016-07-18
Add explicit test for stepping over branches/jumps.
Tim Newsome
1
-0
/
+17
2016-07-18
Make tests work with broken 32-bit compiler.
Tim Newsome
1
-2
/
+6
2016-07-18
Add simple register tests.
Tim Newsome
1
-30
/
+31
2016-07-18
Add block test.
Tim Newsome
2
-2
/
+2
2016-07-18
All tests pass with spike now.
Tim Newsome
3
-4
/
+139
2016-07-18
Made some progress towards working with spike.
Tim Newsome
4
-55
/
+85
2016-07-18
WIP on debug testing.
Tim Newsome
6
-0
/
+181