diff options
Diffstat (limited to 'isa/Makefile')
| -rw-r--r-- | isa/Makefile | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile index 9eef64d..0f0106f 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -18,6 +18,8 @@ include $(src_dir)/rv64uzfh/Makefrag include $(src_dir)/rv64uzba/Makefrag include $(src_dir)/rv64uzbb/Makefrag include $(src_dir)/rv64uzbc/Makefrag +include $(src_dir)/rv64uzbkb/Makefrag +include $(src_dir)/rv64uzbkx/Makefrag include $(src_dir)/rv64uzbs/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64ssvnapot/Makefrag @@ -35,6 +37,8 @@ include $(src_dir)/rv32uzfh/Makefrag include $(src_dir)/rv32uzba/Makefrag include $(src_dir)/rv32uzbb/Makefrag include $(src_dir)/rv32uzbc/Makefrag +include $(src_dir)/rv32uzbkb/Makefrag +include $(src_dir)/rv32uzbkx/Makefrag include $(src_dir)/rv32uzbs/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -70,10 +74,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gch_ziccid_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs_zicclsm $< 2> $@ + $(RISCV_SIM) --isa=rv64gch_ziccid_zfh_zicboz_svnapot_zicntr_zba_zbb_zbkb_zbkx_zbc_zbs_zicclsm $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_ziccid_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs_zicclsm $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_ziccid_zfh_zicboz_svnapot_zicntr_zba_zbb_zbkb_zbkx_zbc_zbs_zicclsm $< 2> $@ define compile_template @@ -111,6 +115,8 @@ $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64d)) $(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64d)) $(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64d)) $(eval $(call compile_template,rv64uzbc,-march=rv64g_zbc -mabi=lp64d)) +$(eval $(call compile_template,rv64uzbkb,-march=rv64g_zbkb -mabi=lp64)) +$(eval $(call compile_template,rv64uzbkx,-march=rv64g_zbkx -mabi=lp64)) $(eval $(call compile_template,rv64uzbs,-march=rv64g_zbs -mabi=lp64d)) $(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64d)) $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64d)) @@ -128,6 +134,8 @@ $(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) $(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) $(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32)) $(eval $(call compile_template,rv32uzbc,-march=rv32g_zbc -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbkb,-march=rv32g_zbkb -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbkx,-march=rv32g_zbkx -mabi=ilp32)) $(eval $(call compile_template,rv32uzbs,-march=rv32g_zbs -mabi=ilp32)) $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) |