diff options
Diffstat (limited to 'debug')
| -rwxr-xr-x | debug/gdbserver.py | 131 | ||||
| -rw-r--r-- | debug/targets.py | 7 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-1.cfg | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-2-hwthread.cfg | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-2.cfg | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-multi.cfg | 4 | ||||
| -rwxr-xr-x | debug/targets/RISC-V/spike32.lds | 9 | ||||
| -rwxr-xr-x | debug/targets/RISC-V/spike64.lds | 9 | ||||
| -rw-r--r-- | debug/testlib.py | 43 |
9 files changed, 160 insertions, 49 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index ba30b9b..92f7ce3 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -11,7 +11,6 @@ import os import re import itertools -from datetime import datetime import targets import testlib from testlib import assertEqual, assertNotEqual @@ -67,6 +66,20 @@ def srec_parse(line): if typ == b'S0': # header return 0, 0, 0 + elif typ == b'S1': + # data with 16-bit address + address = int(line[4:8], 16) + for i in range(4, count+1): + data += f"{int(line[2 * i:2 * i + 2], 16):c}" + # Ignore the checksum. + return 1, address, data + elif typ == b'S2': + # data with 24-bit address + address = int(line[4:10], 16) + for i in range(5, count+1): + data += f"{int(line[2 * i:2 * i + 2], 16):c}" + # Ignore the checksum. + return 2, address, data elif typ == b'S3': # data with 32-bit address # Any higher bits were chopped off. @@ -75,9 +88,9 @@ def srec_parse(line): data += f"{int(line[2 * i:2 * i + 2], 16):c}" # Ignore the checksum. return 3, address, data - elif typ == b'S7': + elif typ in (b'S7', b'S8', b'S9'): # ignore execution start field - return 7, 0, 0 + return int(typ[-1]), 0, 0 else: raise TestFailed(f"Unsupported SREC type {typ!r}.") @@ -265,6 +278,9 @@ class MemTest64(SimpleMemoryTest): class MemTestReadInvalid(SimpleMemoryTest): def test(self): bad_address = self.hart.bad_address + if self.target.support_set_pmp_deny: + self.set_pmp_deny(bad_address) + self.gdb.command("monitor riscv set_mem_access progbuf abstract") good_address = self.hart.ram + 0x80 self.write_nop_program(2) @@ -280,6 +296,10 @@ class MemTestReadInvalid(SimpleMemoryTest): self.gdb.stepi() # Don't let gdb cache register read assertEqual(self.gdb.p(f"*((int*)0x{good_address:x})"), 0xabcdef) assertEqual(self.gdb.p("$s0"), 0x12345678) + if self.target.support_set_pmp_deny: + self.reset_pmp_deny() + self.gdb.command("monitor riscv set_mem_access progbuf sysbus " + "abstract") #class MemTestWriteInvalid(SimpleMemoryTest): # def test(self): @@ -390,7 +410,7 @@ class MemTestBlock(GdbTest): highest_seen = 0 for line in b: record_type, address, line_data = srec_parse(line) - if record_type == 3: + if record_type in (1, 2, 3): offset = address - (self.hart.ram & 0xffffffff) written_data = data[offset:offset+len(line_data)] highest_seen += len(line_data) @@ -677,6 +697,47 @@ class HwbpManual(DebugTest): return self.target.support_manual_hwbp and \ self.hart.instruction_hardware_breakpoint_count >= 1 + # TODO: This can be removed once + # https://github.com/riscv-collab/riscv-openocd/pull/1111 + # is merged. + def check_reserve_trigger_support(self): + not_supp_msg = "RESERVE_TRIGGER_NOT_SUPPORTED" + if not_supp_msg in self.gdb.command( + "monitor if [catch {riscv reserve_trigger 0 on} e] {echo " + + not_supp_msg + "}").splitlines(): + raise TestNotApplicable + + def set_manual_trigger(self, tdata1, tdata2): + for tselect in itertools.count(0): + self.gdb.p(f"$tselect={tselect}") + if self.gdb.p("$tselect") != tselect: + raise TestNotApplicable + + self.gdb.command( + f"monitor riscv reserve_trigger {tselect} on") + + # Need to disable the trigger before writing tdata2 + self.gdb.p("$tdata1=0") + # Need to write a valid value to tdata2 before writing tdata1 + self.gdb.p(f"$tdata2=0x{tdata2:x}") + self.gdb.p(f"$tdata1=0x{tdata1:x}") + + tdata2_rb = self.gdb.p("$tdata2") + tdata1_rb = self.gdb.p("$tdata1") + if tdata1_rb == tdata1 and tdata2_rb == tdata2: + return tselect + + type_rb = tdata1_rb & MCONTROL_TYPE(self.hart.xlen) + type_none = set_field(0, MCONTROL_TYPE(self.hart.xlen), + MCONTROL_TYPE_NONE) + if type_rb == type_none: + raise TestNotApplicable + + self.gdb.p("$tdata1=0") + self.gdb.command( + f"monitor riscv reserve_trigger {tselect} off") + assert False + def test(self): if not self.hart.honors_tdata1_hmode: # Run to main before setting the breakpoint, because startup code @@ -685,6 +746,12 @@ class HwbpManual(DebugTest): self.gdb.c() self.gdb.command("delete") + + # TODO: This can be removed once + # https://github.com/riscv-collab/riscv-openocd/pull/1111 + # is merged. + self.check_reserve_trigger_support() + #self.gdb.hbreak("rot13") tdata1 = MCONTROL_DMODE(self.hart.xlen) tdata1 = set_field(tdata1, MCONTROL_TYPE(self.hart.xlen), @@ -693,24 +760,9 @@ class HwbpManual(DebugTest): tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL) tdata1 |= MCONTROL_M | MCONTROL_S | MCONTROL_U | MCONTROL_EXECUTE - tselect = 0 - while True: - self.gdb.p(f"$tselect={tselect}") - value = self.gdb.p("$tselect") - if value != tselect: - raise TestNotApplicable - # Need to disable the trigger before writing tdata2 - self.gdb.p("$tdata1=0") - # Need to write a valid value to tdata2 before writing tdata1 - self.gdb.p("$tdata2=&rot13") - self.gdb.p(f"$tdata1=0x{tdata1:x}") - value = self.gdb.p("$tdata1") - if value == tdata1: - break - if value & MCONTROL_TYPE(self.hart.xlen) == MCONTROL_TYPE_NONE: - raise TestNotApplicable - self.gdb.p("$tdata1=0") - tselect += 1 + tdata2 = self.gdb.p("&rot13") + + tselect = self.set_manual_trigger(tdata1, tdata2) # The breakpoint should be hit exactly 2 times. for _ in range(2): @@ -727,14 +779,22 @@ class HwbpManual(DebugTest): self.gdb.c() before = self.gdb.p("$pc") assertEqual(before, self.gdb.p("&crc32a")) + self.gdb.stepi() - after = self.gdb.p("$pc") - assertNotEqual(before, after) + assertEqual(before, self.gdb.p("$pc"), + "OpenOCD shouldn't disable a reserved trigger.") # Remove the manual HW breakpoint. assertEqual(tselect, self.gdb.p("$tselect")) self.gdb.p("$tdata1=0") + self.gdb.stepi() + assertNotEqual(before, self.gdb.p("$pc"), + "OpenOCD should be able to step from a removed BP.") + + self.gdb.command( + f"monitor riscv reserve_trigger {tselect} off") + self.gdb.b("_exit") self.exit() @@ -1057,9 +1117,9 @@ class InterruptTest(GdbSingleHartTest): self.disable_timer() return - self.disable_timer() assertGreater(interrupt_count, 1000) assertGreater(local, 1000) + self.disable_timer() def postMortem(self): GdbSingleHartTest.postMortem(self) @@ -2126,8 +2186,13 @@ class EtriggerTest(DebugTest): def test(self): # Set trigger on Load access fault self.gdb.command("monitor riscv etrigger set m 0x20") - # Set fox to a null pointer so we'll get a load access exception later. - self.gdb.p("fox=(char*)0") + # Set fox to a bad pointer so we'll get a load access exception later. + # Use NULL if a known-bad address is not provided. + bad_address = self.hart.bad_address or 0 + if self.target.support_set_pmp_deny: + self.set_pmp_deny(bad_address) + self.gdb.command("monitor riscv set_mem_access progbuf abstract") + self.gdb.p(f"fox=(char*)0x{bad_address:08x}") output = self.gdb.c() # We should not be at handle_trap assertNotIn("handle_trap", output) @@ -2135,6 +2200,10 @@ class EtriggerTest(DebugTest): # actual exception handler. assertIn("breakpoint", output) assertIn("trap_entry", self.gdb.where()) + if self.target.support_set_pmp_deny: + self.reset_pmp_deny() + self.gdb.command("monitor riscv set_mem_access progbuf sysbus " + "abstract") class IcountTest(DebugTest): compile_args = ("programs/infinite_loop.S", ) @@ -2213,14 +2282,6 @@ def main(): module = sys.modules[__name__] - # initialize PRNG - selected_seed = parsed.seed - if parsed.seed is None: - selected_seed = int(datetime.now().timestamp()) - print(f"PRNG seed for {target.name} is generated automatically") - print(f"PRNG seed for {target.name} is {selected_seed}") - random.seed(selected_seed) - return testlib.run_all_tests(module, target, parsed) # TROUBLESHOOTING TIPS diff --git a/debug/targets.py b/debug/targets.py index bb7a5cf..eca0231 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -141,6 +141,13 @@ class Target: # Instruction count limit icount_limit = 4 + # Implements page-based virtual memory. So when PMP changes execute an + # SFENCE.VMA + implements_page_virtual_memory = True + + # Support set_pmp_deny to create invalid addresses. + support_set_pmp_deny = False + # Internal variables: directory = None temporary_files = [] diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg index c6c7d2d..3fdae97 100644 --- a/debug/targets/RISC-V/spike-1.cfg +++ b/debug/targets/RISC-V/spike-1.cfg @@ -5,7 +5,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST) remote_bitbang port $::env(REMOTE_BITBANG_PORT) set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef set _TARGETNAME $_CHIPNAME.cpu if {$::env(USE_FREERTOS)} { diff --git a/debug/targets/RISC-V/spike-2-hwthread.cfg b/debug/targets/RISC-V/spike-2-hwthread.cfg index c10ad8f..5a08ece 100644 --- a/debug/targets/RISC-V/spike-2-hwthread.cfg +++ b/debug/targets/RISC-V/spike-2-hwthread.cfg @@ -6,7 +6,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST) remote_bitbang port $::env(REMOTE_BITBANG_PORT) set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef set _TARGETNAME_0 $_CHIPNAME.cpu0 set _TARGETNAME_1 $_CHIPNAME.cpu1 diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg index ebf3c5a..2de4256 100644 --- a/debug/targets/RISC-V/spike-2.cfg +++ b/debug/targets/RISC-V/spike-2.cfg @@ -6,7 +6,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST) remote_bitbang port $::env(REMOTE_BITBANG_PORT) set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef set _TARGETNAME_0 $_CHIPNAME.cpu0 set _TARGETNAME_1 $_CHIPNAME.cpu1 diff --git a/debug/targets/RISC-V/spike-multi.cfg b/debug/targets/RISC-V/spike-multi.cfg index 36d4328..dff325e 100644 --- a/debug/targets/RISC-V/spike-multi.cfg +++ b/debug/targets/RISC-V/spike-multi.cfg @@ -5,8 +5,8 @@ adapter driver remote_bitbang remote_bitbang host $::env(REMOTE_BITBANG_HOST) remote_bitbang port $::env(REMOTE_BITBANG_PORT) -jtag newtap riscv.0 cpu -irlen 5 -expected-id 0x10e31913 -jtag newtap riscv.1 cpu -irlen 5 -expected-id 0x10e31913 +jtag newtap riscv.0 cpu -irlen 5 -expected-id 0xdeadbeef +jtag newtap riscv.1 cpu -irlen 5 -expected-id 0xdeadbeef target create riscv.0.cpu0 riscv -chain-position riscv.0.cpu -coreid 0 target create riscv.0.cpu1 riscv -chain-position riscv.0.cpu -coreid 1 diff --git a/debug/targets/RISC-V/spike32.lds b/debug/targets/RISC-V/spike32.lds index 77bb1ba..1e3f34f 100755 --- a/debug/targets/RISC-V/spike32.lds +++ b/debug/targets/RISC-V/spike32.lds @@ -5,14 +5,17 @@ SECTIONS /* Leave some space for pk's data structures, which includes tohost/fromhost * which are special addresses we ought to leave alone. */ . = 0x10110000; - .text : + .text : { *(.text.entry) *(.text) + *(.text.*) } /* data segment */ - .data : { *(.data) } + .rodata : { *(.rodata .rodata.*) } + + .data : { *(.data .data.*) } .sdata : { __global_pointer$ = . + 0x800; @@ -27,7 +30,7 @@ SECTIONS *(.sbss .sbss.* .gnu.linkonce.sb.*) *(.scommon) } - .bss : { *(.bss) } + .bss : { *(.bss .bss.*) } __bss_end = .; __malloc_start = .; diff --git a/debug/targets/RISC-V/spike64.lds b/debug/targets/RISC-V/spike64.lds index 2e7d65d..9cbf36f 100755 --- a/debug/targets/RISC-V/spike64.lds +++ b/debug/targets/RISC-V/spike64.lds @@ -3,14 +3,17 @@ OUTPUT_ARCH( "riscv" ) SECTIONS { . = 0x1212340000; - .text : + .text : { *(.text.entry) *(.text) + *(.text.*) } /* data segment */ - .data : { *(.data) } + .rodata : { *(.rodata .rodata.*) } + + .data : { *(.data .data.*) } .sdata : { __global_pointer$ = . + 0x800; @@ -25,7 +28,7 @@ SECTIONS *(.sbss .sbss.* .gnu.linkonce.sb.*) *(.scommon) } - .bss : { *(.bss) } + .bss : { *(.bss .bss.*) } __bss_end = .; __malloc_start = .; diff --git a/debug/testlib.py b/debug/testlib.py index 1f107be..82fe3fb 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -1,6 +1,7 @@ import collections import os import os.path +import random import re import shlex import subprocess @@ -9,6 +10,8 @@ import tempfile import time import traceback +from datetime import datetime + import tty import pexpect import yaml @@ -62,6 +65,7 @@ def compile(args): # pylint: disable=redefined-builtin class Spike: # pylint: disable=too-many-instance-attributes # pylint: disable=too-many-locals + # pylint: disable=too-many-positional-arguments def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True, isa=None, progbufsize=None, dmi_rti=None, abstract_rti=None, support_hasel=True, support_abstract_csr=True, @@ -134,6 +138,9 @@ class Spike: else: isa = f"RV{self.harts[0].xlen}G" + if 'V' in isa[2:]: + isa += f"_Zvl{self.vlen}b_Zve{self.elen}d" + cmd += ["--isa", isa] cmd += ["--dm-auth"] @@ -159,8 +166,6 @@ class Spike: if not self.support_haltgroups: cmd.append("--dm-no-halt-groups") - if 'V' in isa[2:]: - cmd.append(f"--varch=vlen:{self.vlen},elen:{self.elen}") assert len(set(t.ram for t in self.harts)) == 1, \ "All spike harts must have the same RAM layout" @@ -296,6 +301,8 @@ class VcsSim: class Openocd: # pylint: disable=too-many-instance-attributes # pylint: disable-next=consider-using-with + # pylint: disable=too-many-positional-arguments + # pylint: disable=consider-using-with logfile = tempfile.NamedTemporaryFile(prefix='openocd', suffix='.log') logname = logfile.name @@ -713,6 +720,7 @@ class Gdb: 11, 149, 107, 163, 73, 47, 43, 173, 7, 109, 101, 103, 191, 2, 139, 97, 193, 157, 3, 29, 79, 113, 5, 89, 19, 37, 71, 179, 59, 137, 53) + # pylint: disable=too-many-positional-arguments def __init__(self, target, ports, cmd=None, timeout=60, binaries=None, logremote=False): assert ports @@ -1160,6 +1168,14 @@ def run_all_tests(module, target, parsed): excluded_tests = load_excluded_tests(parsed.exclude_tests, target.name) target.skip_tests += excluded_tests + # initialize PRNG + selected_seed = parsed.seed + if parsed.seed is None: + selected_seed = int(datetime.now().timestamp()) + print(f"PRNG seed for {target.name} is generated automatically") + print(f"PRNG seed for {target.name} is {selected_seed}") + random.seed(selected_seed) + results, count = run_tests(parsed, target, todo) header(f"ran {count} tests in {time.time() - overall_start:.0f}s", dash=':') @@ -1292,7 +1308,6 @@ class BaseTest: if not hart is None: self.hart = hart else: - import random # pylint: disable=import-outside-toplevel self.hart = random.choice(target.harts) #self.hart = target.harts[-1] self.server = None @@ -1470,6 +1485,22 @@ class GdbTest(BaseTest): self.gdb.select_hart(self.hart) self.gdb.command(f"monitor targets {self.hart.id}") + def set_pmp_deny(self, address, size=4 * 1024): + # Enable physical memory protection, no permission to access specific + # address range (default 4KB). + self.gdb.p("$mseccfg=0x4") # RLB + self.gdb.p("$pmpcfg0=0x98") # L, NAPOT, !R, !W, !X + self.gdb.p("$pmpaddr0=" + f"0x{((address >> 2) | ((size - 1) >> 3)):x}") + # PMP changes require an sfence.vma, 0x12000073 is sfence.vma + self.gdb.command("monitor riscv exec_progbuf 0x12000073") + + def reset_pmp_deny(self): + self.gdb.p("$pmpcfg0=0") + self.gdb.p("$pmpaddr0=0") + # PMP changes require an sfence.vma, 0x12000073 is sfence.vma + self.gdb.command("monitor riscv exec_progbuf 0x12000073") + def disable_pmp(self): # Disable physical memory protection by allowing U mode access to all # memory. @@ -1483,6 +1514,9 @@ class GdbTest(BaseTest): # pmcfg0 readback matches write, so TOR is supported. self.gdb.p("$pmpaddr0=" f"0x{(self.hart.ram + self.hart.ram_size) >> 2:x}") + if self.target.implements_page_virtual_memory: + # PMP changes require an sfence.vma, 0x12000073 is sfence.vma + self.gdb.command("monitor riscv exec_progbuf 0x12000073") except CouldNotFetch: # PMP registers are optional pass @@ -1493,6 +1527,9 @@ class GdbTest(BaseTest): if interrupt: self.gdb.interrupt() self.gdb.p("$mie=$mie & ~0x80") + self.gdb.p("$mstatus=$mstatus & ~0x8") + self.gdb.p(f"*((long long*) 0x{self.target.clint_addr + 0x4000:x})\ + =0x" + "f" * (self.hart.xlen // 4)) def exit(self, expected_result=10): self.gdb.command("delete") |