8 files changed, 27 insertions, 18 deletions
diff --git a/benchmarks/Makefile b/benchmarks/Makefile
index fde4f23..d38f8af 100644
--- a/benchmarks/Makefile
+++ b/benchmarks/Makefile
@@ -6,6 +6,13 @@
 
 XLEN ?= 64
 
+ifeq ($(XLEN),32)
+ABI ?= ilp32d
+endif
+ifeq ($(XLEN),64)
+ABI ?= lp64d
+endif
+
 default: all
 
 src_dir = .
@@ -43,7 +50,7 @@ bmarks = \
 
 RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf-
 RISCV_GCC ?= $(RISCV_PREFIX)gcc
-RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv$(XLEN)gcv -mabi=lp64d
+RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv$(XLEN)gcv -mabi=$(ABI)
 RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs)
 RISCV_LINK_OPTS ?= -static -nostdlib -nostartfiles -lm -lgcc -T $(src_dir)/common/test.ld
 RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index ba30b9b..235814a 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -11,7 +11,6 @@ import os
 import re
 import itertools
 
-from datetime import datetime
 import targets
 import testlib
 from testlib import assertEqual, assertNotEqual
@@ -2213,14 +2212,6 @@ def main():
 
     module = sys.modules[__name__]
 
-    # initialize PRNG
-    selected_seed = parsed.seed
-    if parsed.seed is None:
-        selected_seed = int(datetime.now().timestamp())
-        print(f"PRNG seed for {target.name} is generated automatically")
-    print(f"PRNG seed for {target.name} is {selected_seed}")
-    random.seed(selected_seed)
-
     return testlib.run_all_tests(module, target, parsed)
 
 # TROUBLESHOOTING TIPS
diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg
index c6c7d2d..3fdae97 100644
--- a/debug/targets/RISC-V/spike-1.cfg
+++ b/debug/targets/RISC-V/spike-1.cfg
@@ -5,7 +5,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST)
 remote_bitbang port $::env(REMOTE_BITBANG_PORT)
 
 set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef
 
 set _TARGETNAME $_CHIPNAME.cpu
 if {$::env(USE_FREERTOS)} {
diff --git a/debug/targets/RISC-V/spike-2-hwthread.cfg b/debug/targets/RISC-V/spike-2-hwthread.cfg
index c10ad8f..5a08ece 100644
--- a/debug/targets/RISC-V/spike-2-hwthread.cfg
+++ b/debug/targets/RISC-V/spike-2-hwthread.cfg
@@ -6,7 +6,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST)
 remote_bitbang port $::env(REMOTE_BITBANG_PORT)
 
 set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef
 
 set _TARGETNAME_0 $_CHIPNAME.cpu0
 set _TARGETNAME_1 $_CHIPNAME.cpu1
diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
index ebf3c5a..2de4256 100644
--- a/debug/targets/RISC-V/spike-2.cfg
+++ b/debug/targets/RISC-V/spike-2.cfg
@@ -6,7 +6,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST)
 remote_bitbang port $::env(REMOTE_BITBANG_PORT)
 
 set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef
 
 set _TARGETNAME_0 $_CHIPNAME.cpu0
 set _TARGETNAME_1 $_CHIPNAME.cpu1
diff --git a/debug/targets/RISC-V/spike-multi.cfg b/debug/targets/RISC-V/spike-multi.cfg
index 36d4328..dff325e 100644
--- a/debug/targets/RISC-V/spike-multi.cfg
+++ b/debug/targets/RISC-V/spike-multi.cfg
@@ -5,8 +5,8 @@ adapter driver remote_bitbang
 remote_bitbang host $::env(REMOTE_BITBANG_HOST)
 remote_bitbang port $::env(REMOTE_BITBANG_PORT)
 
-jtag newtap riscv.0 cpu -irlen 5 -expected-id 0x10e31913
-jtag newtap riscv.1 cpu -irlen 5 -expected-id 0x10e31913
+jtag newtap riscv.0 cpu -irlen 5 -expected-id 0xdeadbeef
+jtag newtap riscv.1 cpu -irlen 5 -expected-id 0xdeadbeef
 
 target create riscv.0.cpu0 riscv -chain-position riscv.0.cpu -coreid 0
 target create riscv.0.cpu1 riscv -chain-position riscv.0.cpu -coreid 1
diff --git a/debug/test b/debug/test
new file mode 100755
index 0000000..9b72737
--- /dev/null
+++ b/debug/test
diff --git a/debug/testlib.py b/debug/testlib.py
index 1f107be..0279b08 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -1,6 +1,7 @@
 import collections
 import os
 import os.path
+import random
 import re
 import shlex
 import subprocess
@@ -9,6 +10,8 @@ import tempfile
 import time
 import traceback
 
+from datetime import datetime
+
 import tty
 import pexpect
 import yaml
@@ -134,6 +137,9 @@ class Spike:
         else:
             isa = f"RV{self.harts[0].xlen}G"
 
+        if 'V' in isa[2:]:
+            isa += f"_Zvl{self.vlen}b_Zve{self.elen}d"
+
         cmd += ["--isa", isa]
         cmd += ["--dm-auth"]
 
@@ -159,8 +165,6 @@ class Spike:
         if not self.support_haltgroups:
             cmd.append("--dm-no-halt-groups")
 
-        if 'V' in isa[2:]:
-            cmd.append(f"--varch=vlen:{self.vlen},elen:{self.elen}")
 
         assert len(set(t.ram for t in self.harts)) == 1, \
                 "All spike harts must have the same RAM layout"
@@ -1160,6 +1164,14 @@ def run_all_tests(module, target, parsed):
     excluded_tests = load_excluded_tests(parsed.exclude_tests, target.name)
     target.skip_tests += excluded_tests
 
+    # initialize PRNG
+    selected_seed = parsed.seed
+    if parsed.seed is None:
+        selected_seed = int(datetime.now().timestamp())
+        print(f"PRNG seed for {target.name} is generated automatically")
+    print(f"PRNG seed for {target.name} is {selected_seed}")
+    random.seed(selected_seed)
+
     results, count = run_tests(parsed, target, todo)
 
     header(f"ran {count} tests in {time.time() - overall_start:.0f}s", dash=':')
@@ -1292,7 +1304,6 @@ class BaseTest:
         if not hart is None:
             self.hart = hart
         else:
-            import random   # pylint: disable=import-outside-toplevel
             self.hart = random.choice(target.harts)
             #self.hart = target.harts[-1]
         self.server = None