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| author | liangzhen <zhen.liang@spacemit.com> | 2023-10-24 09:29:53 +0800 |
|---|---|---|
| committer | liangzhen <zhen.liang@spacemit.com> | 2023-10-24 09:29:53 +0800 |
| commit | aa15f70c071a03b428621990142f6c049a656526 (patch) | |
| tree | 57b4de30f25448454476fd93cd5dcc5d43336b55 /debug/targets.py | |
| parent | d020e2069a9f6a9c0e875f23f0f4aababea9fbf0 (diff) | |
| download | riscv-tests-aa15f70c071a03b428621990142f6c049a656526.zip riscv-tests-aa15f70c071a03b428621990142f6c049a656526.tar.gz riscv-tests-aa15f70c071a03b428621990142f6c049a656526.tar.bz2 | |
Support instruction count limit in IcountTest
This is taking into account that the hardware limits count to 1.
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/debug/targets.py b/debug/targets.py index 189d79b..bb7a5cf 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -138,6 +138,9 @@ class Target: # Supports controlling hart availability through DMCUSTOM. support_unavailable_control = False + # Instruction count limit + icount_limit = 4 + # Internal variables: directory = None temporary_files = [] |