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| author | liangzhen <zhen.liang@spacemit.com> | 2023-10-24 09:29:53 +0800 |
|---|---|---|
| committer | liangzhen <zhen.liang@spacemit.com> | 2023-10-24 09:29:53 +0800 |
| commit | aa15f70c071a03b428621990142f6c049a656526 (patch) | |
| tree | 57b4de30f25448454476fd93cd5dcc5d43336b55 | |
| parent | d020e2069a9f6a9c0e875f23f0f4aababea9fbf0 (diff) | |
| download | riscv-tests-aa15f70c071a03b428621990142f6c049a656526.zip riscv-tests-aa15f70c071a03b428621990142f6c049a656526.tar.gz riscv-tests-aa15f70c071a03b428621990142f6c049a656526.tar.bz2 | |
Support instruction count limit in IcountTest
This is taking into account that the hardware limits count to 1.
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
| -rwxr-xr-x | debug/gdbserver.py | 8 | ||||
| -rw-r--r-- | debug/targets.py | 3 |
2 files changed, 9 insertions, 2 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 86359c8..5450adb 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -2129,9 +2129,13 @@ class IcountTest(DebugTest): def test(self): # Execute 2 instructions. output = self.gdb.command("monitor riscv icount set m 2") - assertNotIn("Failed", output) + if self.target.icount_limit > 1: + assertNotIn("Failed", output) + else: + assertIn("Failed", output) + self.gdb.b("main_post_csrr") output = self.gdb.c() - assertIn("breakpoint", output) + assertIn("main_post_csrr", output) main_post_csrr = self.gdb.p("&main_post_csrr") assertEqual(self.gdb.p("$pc"), main_post_csrr) diff --git a/debug/targets.py b/debug/targets.py index 189d79b..bb7a5cf 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -138,6 +138,9 @@ class Target: # Supports controlling hart availability through DMCUSTOM. support_unavailable_control = False + # Instruction count limit + icount_limit = 4 + # Internal variables: directory = None temporary_files = [] |