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| author | Tim Newsome <tim@sifive.com> | 2023-07-07 15:08:12 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-07 15:08:12 -0700 |
| commit | fb7a4a7a0e1372cde0e920d75679ba1541e52c77 (patch) | |
| tree | 9ecdd97530adf95b24359d1f3c4ef8d69dbcc946 /debug/Makefile | |
| parent | 1f7a4b409a495f479b57a625922b6dbfa55b9122 (diff) | |
| parent | 77d04b06ae509ca739dd16368a5b89a192a25bf0 (diff) | |
| download | riscv-tests-fb7a4a7a0e1372cde0e920d75679ba1541e52c77.zip riscv-tests-fb7a4a7a0e1372cde0e920d75679ba1541e52c77.tar.gz riscv-tests-fb7a4a7a0e1372cde0e920d75679ba1541e52c77.tar.bz2 | |
Merge pull request #487 from riscv-software-src/debug_path
debug: Don't rely on RISCV env
Diffstat (limited to 'debug/Makefile')
| -rw-r--r-- | debug/Makefile | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/debug/Makefile b/debug/Makefile index 172defe..5741362 100644 --- a/debug/Makefile +++ b/debug/Makefile @@ -1,4 +1,3 @@ -RISCV_SIM ?= spike XLEN ?= 64 src_dir ?= . @@ -22,8 +21,6 @@ run.%: $(word 3, $(subst ., ,$@)) \ --isolate \ --print-failures \ - --sim_cmd $(RISCV)/bin/$(RISCV_SIM) \ - --server_cmd $(RISCV)/bin/openocd \ $(if $(EXCLUDE_TESTS),--exclude-tests $(EXCLUDE_TESTS)) # Target to check all the multicore options. |