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| author | Tim Newsome <tim@sifive.com> | 2023-07-07 15:08:12 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-07 15:08:12 -0700 |
| commit | fb7a4a7a0e1372cde0e920d75679ba1541e52c77 (patch) | |
| tree | 9ecdd97530adf95b24359d1f3c4ef8d69dbcc946 | |
| parent | 1f7a4b409a495f479b57a625922b6dbfa55b9122 (diff) | |
| parent | 77d04b06ae509ca739dd16368a5b89a192a25bf0 (diff) | |
| download | riscv-tests-fb7a4a7a0e1372cde0e920d75679ba1541e52c77.zip riscv-tests-fb7a4a7a0e1372cde0e920d75679ba1541e52c77.tar.gz riscv-tests-fb7a4a7a0e1372cde0e920d75679ba1541e52c77.tar.bz2 | |
Merge pull request #487 from riscv-software-src/debug_path
debug: Don't rely on RISCV env
| -rw-r--r-- | debug/Makefile | 3 | ||||
| -rw-r--r-- | debug/README.md | 9 |
2 files changed, 4 insertions, 8 deletions
diff --git a/debug/Makefile b/debug/Makefile index 172defe..5741362 100644 --- a/debug/Makefile +++ b/debug/Makefile @@ -1,4 +1,3 @@ -RISCV_SIM ?= spike XLEN ?= 64 src_dir ?= . @@ -22,8 +21,6 @@ run.%: $(word 3, $(subst ., ,$@)) \ --isolate \ --print-failures \ - --sim_cmd $(RISCV)/bin/$(RISCV_SIM) \ - --server_cmd $(RISCV)/bin/openocd \ $(if $(EXCLUDE_TESTS),--exclude-tests $(EXCLUDE_TESTS)) # Target to check all the multicore options. diff --git a/debug/README.md b/debug/README.md index 7dd6790..b98d8c2 100644 --- a/debug/README.md +++ b/debug/README.md @@ -9,11 +9,10 @@ confident that the actual debug interface is functioning correctly. Requirements ============ The following should be in the user's path: -* riscv64-unknown-elf-gcc (`rvv-0.9.x` branch for riscv-gnu-toolchain should - work if master does not have vector support yet) -* riscv64-unknown-elf-gdb (can be overridden with `--gdb` when running - gdbserver.py manually), which should be the latest from - git://sourceware.org/git/binutils-gdb.git. +* riscv64-unknown-elf-gcc (GCC 12 and later should work). If your binary has a + different name, you can set the RISCV_TESTS_DEBUG_GCC environment variable. +* riscv64-unknown-elf-gdb. If your binary has a + different name, you can set the RISCV_TESTS_DEBUG_GDB environment variable. * spike (can be overridden with `--sim_cmd` when running gdbserver.py manually), which should be the latest from https://github.com/riscv/riscv-isa-sim.git. |