From fd01e46314636666b5bed1f08465f734751a4cda Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 19 Mar 2024 14:14:31 -0700 Subject: ma_addr: permit access faults in lieu of misaligned exceptions --- isa/rv64mi/ma_addr.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index f02a1af..8579c01 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -20,6 +20,7 @@ RVTEST_CODE_BEGIN # indicate it's a load test li s1, CAUSE_MISALIGNED_LOAD + li s2, CAUSE_LOAD_ACCESS #define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1))) @@ -56,6 +57,7 @@ RVTEST_CODE_BEGIN # indicate it's a store test li s1, CAUSE_MISALIGNED_STORE + li s2, CAUSE_STORE_ACCESS /* Check that a misaligned store has some effect and takes no exception, or takes no effect and generates an exception. This is not very @@ -96,7 +98,10 @@ RVTEST_CODE_BEGIN .global mtvec_handler mtvec_handler: csrr t0, mcause - bne t0, s1, fail + beq t0, s1, 1f + beq t0, s2, 1f + j fail +1: csrr t0, mbadaddr beqz t0, 1f -- cgit v1.1