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| author | Tim Newsome <tim@sifive.com> | 2023-07-05 08:18:32 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-05 08:18:32 -0700 |
| commit | 1f7a4b409a495f479b57a625922b6dbfa55b9122 (patch) | |
| tree | 6da664a2419b11283d780ac60d927d22156964a4 | |
| parent | 10a93cb7234c419aa7afcc8361a1d78fc38993d7 (diff) | |
| parent | fd294ae0fde0840272b54a31024551233f576090 (diff) | |
| download | riscv-tests-1f7a4b409a495f479b57a625922b6dbfa55b9122.zip riscv-tests-1f7a4b409a495f479b57a625922b6dbfa55b9122.tar.gz riscv-tests-1f7a4b409a495f479b57a625922b6dbfa55b9122.tar.bz2 | |
Merge pull request #484 from TommyMurphyTM1234/master
Fix for test program compilation failures due to lack of `zicsr` extension in `-march=rvXX...`
| -rw-r--r-- | debug/targets.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/debug/targets.py b/debug/targets.py index 0ba12db..1952749 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -196,7 +196,7 @@ class Target: "-o", binary_name] if hart.extensionSupported('e'): - args.append("-march=rv32e") + args.append("-march=rv32e_zicsr") args.append("-mabi=ilp32e") args.append("-DRV32E") else: @@ -206,7 +206,7 @@ class Target: march += letter if hart.extensionSupported("v") and self.compiler_supports_v: march += "v" - args.append(f"-march={march}") + args.append(f"-march={march}_zicsr") if hart.xlen == 32: args.append("-mabi=ilp32") else: |