From 36b18c8e4ea7bdcd30aed03c5d6235fbb0f8213c Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Sun, 18 Feb 2024 20:16:38 -0800
Subject: Fix breakpoint test

See https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214
---
 isa/rv64mi/breakpoint.S | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S
index 1223f71..153963a 100644
--- a/isa/rv64mi/breakpoint.S
+++ b/isa/rv64mi/breakpoint.S
@@ -26,6 +26,9 @@ RVTEST_CODE_BEGIN
 1:
   csrw mtvec, a0
 
+  # Enable interrupts; see https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214
+  csrsi mstatus, MSTATUS_MIE
+
   # Skip tselect if hard-wired.
   csrw tselect, x0
   csrr a1, tselect
-- 
cgit v1.1