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| author | Tommy Murphy <tommy_murphy@hotmail.com> | 2023-06-30 10:29:37 +0100 |
|---|---|---|
| committer | Tommy Murphy <tommy_murphy@hotmail.com> | 2023-06-30 10:29:37 +0100 |
| commit | fd294ae0fde0840272b54a31024551233f576090 (patch) | |
| tree | b651d581a9e6b8eabbb46c9a19d620d22240fd1a | |
| parent | 247e2334ef60654ad53ca1dd0a688dc1f0fccd33 (diff) | |
| download | riscv-tests-fd294ae0fde0840272b54a31024551233f576090.zip riscv-tests-fd294ae0fde0840272b54a31024551233f576090.tar.gz riscv-tests-fd294ae0fde0840272b54a31024551233f576090.tar.bz2 | |
Fix for https://github.com/riscv-software-src/riscv-tests/issues/482
| -rw-r--r-- | debug/targets.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/debug/targets.py b/debug/targets.py index 0ba12db..1952749 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -196,7 +196,7 @@ class Target: "-o", binary_name] if hart.extensionSupported('e'): - args.append("-march=rv32e") + args.append("-march=rv32e_zicsr") args.append("-mabi=ilp32e") args.append("-DRV32E") else: @@ -206,7 +206,7 @@ class Target: march += letter if hart.extensionSupported("v") and self.compiler_supports_v: march += "v" - args.append(f"-march={march}") + args.append(f"-march={march}_zicsr") if hart.xlen == 32: args.append("-mabi=ilp32") else: |