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# TI OMAP3530
# http://focus.ti.com/docs/prod/folders/print/omap3530.html
# Other OMAP3 chips remove DSP and/or the OpenGL support
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME omap3530
}
# ICEpick-C ... used to route Cortex, DSP, and more not shown here
source [find target/icepick.cfg]
# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
# Subsidiary TAP: CoreSight Debug Access Port (DAP)
if { [info exists DAP_TAPID ] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x0b6d602f
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID ] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b7ae02f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID
# GDB target: Cortex-A8, using DAP
# FIXME when we have A8 support, use it. A8 != M3 ...
target create omap3.cpu cortex_m3 -chain-position $_CHIPNAME.dap
# FIXME much of this should be in reset event handlers
proc omap3_dbginit { } {
reset
sleep 500
jtag tapenable omap3530.dap
targets
# sleep 1000
# dap apsel 1
# sleep 1000
# dap apsel 1
# dap info 1
# 0xd401.0000 - ETM
# 0xd401.1000 - Cortex-A8
# 0xd401.9000 - TPIU (traceport)
# 0xd401.b000 - ETB
# 0xd401.d000 - DAPCTL
omap3.cpu mww 0x54011FB0 0xC5ACCE55
omap3.cpu mdw 0x54011314
omap3.cpu mdw 0x54011314
# omap3.cpu mdw 0x54011080
omap3.cpu mww 0x5401d030 0x00002000
}
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