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# SPDX-License-Identifier: GPL-2.0-or-later
#
# NXP i.MX8QuadMax
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imx8qm
}
# CoreSight Debug Access Port (DAP)
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
# TAPID is from FreeScale!
set _DAP_TAPID 0x1890101d
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
# AXI: Main SOC bus on AP #0
target create ${_CHIPNAME}.axi mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
# 4x Cortex-A53 on AP #6
set _A53_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
set _A53_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
cti create $_CHIPNAME.a53_cti.0 -dap $_CHIPNAME.dap \
-ap-num 6 -baseaddr [lindex $_A53_CTIBASE 0]
cti create $_CHIPNAME.a53_cti.1 -dap $_CHIPNAME.dap \
-ap-num 6 -baseaddr [lindex $_A53_CTIBASE 1]
cti create $_CHIPNAME.a53_cti.2 -dap $_CHIPNAME.dap \
-ap-num 6 -baseaddr [lindex $_A53_CTIBASE 2]
cti create $_CHIPNAME.a53_cti.3 -dap $_CHIPNAME.dap \
-ap-num 6 -baseaddr [lindex $_A53_CTIBASE 3]
target create $_CHIPNAME.a53.0 aarch64 -dap $_CHIPNAME.dap \
-cti $_CHIPNAME.a53_cti.0 -dbgbase [lindex $_A53_DBGBASE 0]
target create $_CHIPNAME.a53.1 aarch64 -dap $_CHIPNAME.dap \
-cti $_CHIPNAME.a53_cti.1 -dbgbase [lindex $_A53_DBGBASE 1] -defer-examine
target create $_CHIPNAME.a53.2 aarch64 -dap $_CHIPNAME.dap \
-cti $_CHIPNAME.a53_cti.2 -dbgbase [lindex $_A53_DBGBASE 2] -defer-examine
target create $_CHIPNAME.a53.3 aarch64 -dap $_CHIPNAME.dap \
-cti $_CHIPNAME.a53_cti.3 -dbgbase [lindex $_A53_DBGBASE 3] -defer-examine
# 2x Cortex-A72 on AP #6
set _A72_DBGBASE {0x80210000 0x80310000}
set _A72_CTIBASE {0x80220000 0x80220000}
cti create $_CHIPNAME.a72_cti.0 -dap $_CHIPNAME.dap \
-ap-num 6 -baseaddr [lindex $_A72_CTIBASE 0]
cti create $_CHIPNAME.a72_cti.1 -dap $_CHIPNAME.dap \
-ap-num 6 -baseaddr [lindex $_A72_CTIBASE 1]
target create $_CHIPNAME.a72.0 aarch64 -dap $_CHIPNAME.dap \
-cti $_CHIPNAME.a72_cti.0 -dbgbase [lindex $_A72_DBGBASE 0] -defer-examine
target create $_CHIPNAME.a72.1 aarch64 -dap $_CHIPNAME.dap \
-cti $_CHIPNAME.a72_cti.1 -dbgbase [lindex $_A72_DBGBASE 1] -defer-examine
# All Cortex-A in SMP
target smp \
$_CHIPNAME.a53.0 \
$_CHIPNAME.a53.1 \
$_CHIPNAME.a53.2 \
$_CHIPNAME.a53.3 \
$_CHIPNAME.a72.0 \
$_CHIPNAME.a72.1
# SCU: Cortex-M4 core
# always running imx SC firmware
target create ${_CHIPNAME}.scu cortex_m -dap ${_CHIPNAME}.dap -ap-num 1
# AHB from SCU perspective
target create ${_CHIPNAME}.scu_ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 4
# Cortex-M4 M4_0 core on AP #2 (default off)
target create ${_CHIPNAME}.m4_0 cortex_m -dap ${_CHIPNAME}.dap -ap-num 2 \
-defer-examine
# Cortex-M4 M4_1 core on AP #3 (default off)
target create ${_CHIPNAME}.m4_1 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3 \
-defer-examine
# Debug APB bus
target create ${_CHIPNAME}.apb mem_ap -dap ${_CHIPNAME}.dap -ap-num 6
# Default target is boot core a53.0
targets $_CHIPNAME.a53.0
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