1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
|
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an STM32F413H discovery board with a single STM32F413ZHT6 chip.
# http://www.st.com/en/evaluation-tools/32f413hdiscovery.html
#
# Untested!!!
#
# This is for using the onboard STLINK
source [find interface/stlink.cfg]
transport select hla_swd
# increase working area to 128KB
set WORKAREASIZE 0x20000
# enable stmqspi
set QUADSPI 1
source [find target/stm32f4x.cfg]
# QUADSPI initialization
proc qspi_init { } {
global a
mmw 0x40023830 0x000000FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)
mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
sleep 1 ;# Wait for clock startup
# PG06: BK1_NCS, PB02: CLK, PD13: BK1_IO3, PE02: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
# PB02:AF09:V, PD13:AF09:V, PE02:AF09:V, PF09:AF10:V, PF08:AF10:V, PG06:AF10:V
# Port B: PB02:AF09:V
mmw 0x40020400 0x00000020 0x00000010 ;# MODER
mmw 0x40020408 0x00000030 0x00000000 ;# OSPEEDR
mmw 0x40020420 0x00000900 0x00000600 ;# AFRL
# Port D: PD13:AF09:V
mmw 0x40020C00 0x08000000 0x04000000 ;# MODER
mmw 0x40020C08 0x0C000000 0x00000000 ;# OSPEEDR
mmw 0x40020C24 0x00900000 0x00600000 ;# AFRH
# Port E: PE02:AF09:V
mmw 0x40021000 0x00000020 0x00000010 ;# MODER
mmw 0x40021008 0x00000030 0x00000000 ;# OSPEEDR
mmw 0x40021020 0x00000900 0x00000600 ;# AFRL
# Port F: PF09:AF10:V, PF08:AF10:V
mmw 0x40021400 0x000A0000 0x00050000 ;# MODER
mmw 0x40021408 0x000F0000 0x00000000 ;# OSPEEDR
mmw 0x40021424 0x000000AA 0x00000055 ;# AFRH
# Port G: PG06:AF10:V
mmw 0x40021800 0x00002000 0x00001000 ;# MODER
mmw 0x40021808 0x00003000 0x00000000 ;# OSPEEDR
mmw 0x40021820 0x0A000000 0x05000000 ;# AFRL
mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
mww 0xA0001004 0x00170100 ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1
# 1-line spi mode
mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
sleep 1
# memory-mapped read mode with 3-byte addresses
mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
}
$_TARGETNAME configure -event reset-init {
mww 0x40023C00 0x00000003 ;# 3 WS for 96 MHz HCLK
sleep 1
mww 0x40023804 0x24001808 ;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2
mww 0x40023808 0x00001000 ;# APB1: /2, APB2: /1
mmw 0x40023800 0x01000000 0x00000000 ;# PLL on
sleep 1
mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL
sleep 1
adapter speed 4000
qspi_init
}
|
