blob: 3d934073507ac7e0dcf0d05d8819ecdc711b4e0b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
# Copyright (C) 2014-2016,2020 Synopsys, Inc.
# Anton Kolesov <anton.kolesov@synopsys.com>
# Didin Evgeniy <didin@synopsys.com>
#
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Synopsys DesignWare ARC EM Starter Kit v2.x
#
# Configure JTAG cable
# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
source [find interface/ftdi/digilent-hs1.cfg]
# 5MHz seems to work good with all cores that might happen in 2.x
adapter speed 5000
# ARCs support only JTAG.
transport select jtag
# Configure FPGA. This script supports both LX45 and LX150.
source [find target/snps_em_sk_fpga.cfg]
|