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# Target configuration for the Samsung s3c6410 system on chip
# Tested on a tiny6410
# Processor : ARM1176
# Info : JTAG tap: s3c6410.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: 0xb900, ver: 0x2)
# Info : JTAG tap: s3c6410.cpu tap/device found: 0x07b76f0f (mfg: 0x787, part: 0x7b76, ver: 0x0)
source [find target/samsung_s3c6410.cfg]
proc init_6410 {} {
halt
reg cpsr 0x1D3
arm mcr 15 0 15 2 4 0x70000013
#-----------------------------------------------
# Clock and Timer Setting
#-----------------------------------------------
mww 0x7e004000 0 ;# WATCHDOG - Disable
mww 0x7E00F120 0x0003 ;# MEM_SYS_CFG - CS0:8 bit, Mem1:32bit, CS2=NAND
#mww 0x7E00F120 0x1000 ;# MEM_SYS_CFG - CS0:16bit, Mem1:32bit, CS2=SROMC
#mww 0x7E00F120 0x1002 ;# MEM_SYS_CFG - CS0:16bit, Mem1:32bit, CS2=OND
mww 0x7E00F900 0x805e ;# OTHERS - Change SYNCMUX[6] to “1”
sleep 1000
mww 0x7E00F900 0x80de ;# OTHERS - Assert SYNCREQ&VICSYNCEN to “1”(rb1004modify)
sleep 1000 ;# - Others[11:8] to 0xF
mww 0x7E00F000 0xffff ;# APLL_LOCK - APLL LockTime
mww 0x7E00F004 0xffff ;# MPLL_LOCK - MPLL LockTime
mww 0x7E00F020 0x1047310 ;# CLK_DIV0 - ARMCLK:HCLK:PCLK = 1:4:16
mww 0x7E00F00c 0x81900302 ;# APLL_CON - A:400, P:3, S:2 => 400MHz
mww 0x7E00F010 0x81900303 ;# MPLL_CON - M:400, P:3, S:3 => 200MHz
mww 0x7E00F01c 0x3 ;# CLK_SRC - APLL,MPLL Clock Select
#-----------------------------------------------
# DRAM initialization
#-----------------------------------------------
mww 0x7e001004 0x4 ;# P1MEMCCMD - Enter the config state
mww 0x7e001010 0x30C ;# P1REFRESH - Refresh Period register (7800ns), 100MHz
# mww 0x7e001010 0x40e ;# P1REFRESH - Refresh Period register (7800ns), 133MHz
mww 0x7e001014 0x6 ;# P1CASLAT - CAS Latency = 3
mww 0x7e001018 0x1 ;# P1T_DQSS
mww 0x7e00101c 0x2 ;# P1T_MRD
mww 0x7e001020 0x7 ;# P1T_RAS - 45 ns
mww 0x7e001024 0xA ;# P1T_RC - 67.5 ns
mww 0x7e001028 0xC ;# P1T_RCD - 22.5 ns
mww 0x7e00102C 0x10B ;# P1T_RFC - 80 ns
mww 0x7e001030 0xC ;# P1T_RP - 22.5 ns
mww 0x7e001034 0x3 ;# P1T_RRD - 15 ns
mww 0x7e001038 0x3 ;# P1T_WR - 15 ns
mww 0x7e00103C 0x2 ;# P1T_WTR
mww 0x7e001040 0x2 ;# P1T_XP
mww 0x7e001044 0x11 ;# P1T_XSR - 120 ns
mww 0x7e001048 0x11 ;# P1T_ESR
#-----------------------------------------------
# Memory Configuration Registers
#-----------------------------------------------
mww 0x7e00100C 0x00010012 ;# P1MEMCFG - 1 CKE, 1Chip, 4burst, Alw, AP[10],ROW/Column bit
mww 0x7e00104C 0x0B41 ;# P1MEMCFG2 - Read delay 1 Cycle, mDDR, 32bit, Sync.
mww 0x7e001200 0x150F0 ;# CHIP_N_CFG - 0x150F0 for 256M, 0x150F8 for 128M
#-----------------------------------------------
# Memory Direct Commands
#-----------------------------------------------
mww 0x7e001008 0xc0000 ;# Chip0 Direct Command :NOP5
mww 0x7e001008 0x0 ;# Chip0 Direct Command :PreCharge al
mww 0x7e001008 0x40000 ;# Chip0 Direct Command :AutoRefresh
mww 0x7e001008 0x40000 ;# Chip0 Direct Command :AutoRefresh
mww 0x7e001008 0xA0000 ;# EMRS, DS:Full, PASR:Full
mww 0x7e001008 0x80032 ;# MRS, CAS3, BL4
mww 0x7e001004 0x0 ;# Enable DMC1
}
proc install_6410_uboot {} {
# write U-boot magic number
mww 0x50000000 0x24564236
mww 0x50000004 0x20764316
load_image u-boot_nand-ram256.bin 0x50008000 bin
load_image u-boot_nand-ram256.bin 0x57E00000 bin
#Kick in
reg pc 0x57E00000
resume
}
proc init_6410_flash {} {
halt
nand probe 0
nand list
}
adapter_khz 1000
adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
gdb_breakpoint_override hard
targets
nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu
init
echo " "
echo " "
echo "-------------------------------------------------------------------"
echo "---- The following mini6410/tiny6410 functions are available: ----"
echo "---- init_6410 - initialize clock, timer, DRAM ----"
echo "---- init_6410_flash - initializes NAND flash support ----"
echo "---- install_6410_uboot - copies u-boot image into RAM and ----"
echo "---- runs it ----"
echo "-------------------------------------------------------------------"
echo " "
echo " "
|
