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2021-11-15flash/nor/stm32f1x: Add support for GD32E23xasier701-0/+74
GD32E23x from GigaDevice is cortex-M23 microcontroller and it can work with the stm32f1x driver. Modifications are similar to this done for GD32F1x0 in #6164 (https://review.openocd.org/c/openocd/+/6164). Configuration file is added because its cortex-M23 CPU ID is different. I think that GigaDevice microcontrollers should be handled in an independent unit to separate them from STM32, but nowadays quick solution is welcome. Signed-off-by: asier70Andrzej Sierżęga <asier70@gmail.com> Change-Id: I91f31f5f66808bc50a8f607ac2c107e6b7c5e2b8 Reviewed-on: https://review.openocd.org/c/openocd/+/6527 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-10-25tcl/stm32mp15x: freeze watchdog, recover SWD after power cycleAntonio Borneo1-1/+4
Freeze the IWDG watchdog when cores are halted to prevent a reset while debugging. The PMIC present on some board senses the nsrst and forces a power cycle to the target. The power cycle causes the SWJ-DP to restart in JTAG mode. If the debugger is using SWD, the mismatch triggers an error after the reset command. Ignore the error detected by 'dap init' and proceed executing the handler. The error in 'dap init' will force a reconnect during the following 'dap apid', restoring the SWD functionality. Change-Id: I04fcda6a5b8a1b080ab4e8890ecd0754d5ed12d9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6599 Tested-by: jenkins
2021-09-25tcl/stm32wlx.cfg: comply with new jimtcl expr syntaxTarek BOCHKATI1-1/+1
Change-Id: I2e9fd528817b14396c7643801aeea5c8dde668e0 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6557 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2021-09-17tcl/target/stm32(f7/h7)x: do not assume presence of the resetTarek BOCHKATI2-2/+2
do not force the presence of the reset line, since some custom boards may do not contain the reset line. Change-Id: I031ab34012b34a1b49def9db16461f9de0ae29cc Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reported-by: Fleck <fleckz@users.sourceforge.net> Fixes: https://sourceforge.net/p/openocd/tickets/316/ Reviewed-on: https://review.openocd.org/c/openocd/+/6506 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2021-09-02flash/nor: add support for Nuvoton NPCX series flashWealian Liao1-0/+51
Added NPCX flash driver to support the Nuvoton NPCX series microcontrollers. Add config file for NPCX series. Change-Id: Ia10b019a3521f59ad1e10ccdc56827ba30c3eac8 Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com> Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5950 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-08-30flash/stm32l4x: add support of STM32U57x/U58xTarek BOCHKATI1-0/+207
this device flash registers are quite similar to STM32L5 with this changes : - flash size is up to 2MB - 2MB variants are always dual bank - 1MB and 512KB variants could be dual bank (contiguous addressing) depending on DUALBANK bit(21) - flash data width is 16 bytes (quad-word) Change-Id: Id13c552270ce1071479ad418526e8a39ebe83cb1 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6108 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-08-26flash/stm32l4x: add support of STM32WL5x dual coreTarek BOCHKATI1-28/+115
according the RM0453, the second core have a different Flash CR and SR registers for flash operations (called C2CR and C2SR). so we need to a different flash_regs than older L4 devices. @see stm32wl_cpu2_flash_regs the C2CR register don't contain LOCK and OPTLOCK bits, and this explain the addition of new register index called STM32_FLASH_CR_WLK_INDEX to look-up the CR with lock, to be used in locking/unlocking the flash. note: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1, to solve this read the UID64 (IEEE 64-bit unique device ID register) Change-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6050 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-08-26flash/stm32l4x: STM32L5 support programming when TZEN=1 and RDP=0x55Tarek BOCHKATI1-1/+5
when RDP level is 0.5 the provided work-area should reside in non-secure RAM to ensure that: - add a hint in the driver level - reduce the usage of secure RAM only when TZEN=1 and RDP is not 0.5 (check the target configuration file) Change-Id: Idbf2325e609b84ef8480eefdb49a176fdf7e07c7 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6035 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins
2021-08-26flash/stm32l4x: STM32L5 support programming when TZEN=1 and RDP=0xAATarek BOCHKATI1-12/+77
STM32L5 flash memory is aliased to 0x0C000000, this address mapping is used for secure applications. (0x08000000 for non-secure) this change allows the programming of secure and non-secure flash when trustzone is enabled and RDP level is 0 Change-Id: I89d1f1b5d493cf01a142ca4dbfef5a3731cab96e Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5936 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-08-14add config for Microchip SAMA5D27 SOM1 Kit1Oleksij Rempel1-0/+28
... and related SAMA5D27 SoC. Change-Id: Ic2584e3005ac691642dc2e5a8ee3fb8a4eacaa00 Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-on: http://openocd.zylin.com/5275 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-06-26tcl/target: Add support for Renesas R8A779A0 V3U SoCMarek Vasut1-16/+41
The V3U SoC is unique in that it now has 8x CA76 and CR52, while the previous SoCs had CA57/CA53/CR7 . This can still be handled without too complex modifications to the gen3 configuration file, so add the logic to handle it there. Change-Id: I7ab33eacc1fd379d369988d3d6690d2e82346c7e Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/6314 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-26tcl/target: Select default boot core on Renesas R-Car Gen2/Gen3Marek Vasut2-0/+6
On SMP Renesas R-Car Gen2/Gen3 systems, select the boot core as the default target using the 'targets' command. This way, the user can start debugging code running on the boot core without having to switch to the boot core by explicitly invoking 'targets' command first, since it is likely the debugged code will run on the boot core. Note that most of the code is already in place, it was just not used, so this is more of a fix to make the original intention work. Change-Id: I727808adce617c1d9ebd6ffa34f60f5882cdae60 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/6313 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-04target/renesas_rz_g2: Introduce tcl config file for RZ/G2 devicesmicbis1-0/+185
Initial support for Renesas RZ/G2 MPU family Change-Id: I5ca74cddfd0c105a5307de56c3ade7084f9c28d2 Signed-off-by: micbis <michele.bisogno.ct@renesas.com> Reviewed-on: http://openocd.zylin.com/6250 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-04tcl/target/stm32f4x: fix hardcoded chip nameTarek BOCHKATI1-1/+1
Fixes: c945d6e61605 ("tcl/target: start using the new TPIU/SWO support") Change-Id: I4543c9a204f7b4b3b14e6eabc5042653106aff0e Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/6277 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2021-05-22target/zynqmp : Add AXI AP access portOlivier DANET1-0/+2
The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs. Change-Id: I6303331c217795657575de4759444938e775dee1 Signed-off-by: Olivier DANET <odanet@caramail.com> Reviewed-on: http://openocd.zylin.com/6263 Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-22tcl: fix some minor typoAntonio Borneo5-10/+10
Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. While there, fix one indentation. Change-Id: I72369ed26f363bacd760b40b8c83dd95e89d28a4 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6214 Tested-by: jenkins
2021-05-22tcl/rp2040: remove empty line at end of fileAntonio Borneo1-1/+0
Change-Id: I212a96b77282b151a8ecbd46a6436e2bbbda4161 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6221 Tested-by: jenkins
2021-05-08tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax changeAntonio Borneo12-47/+47
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. Fix manually the remaining lines that don't match simple patterns and would require dedicated boring scripting. Remove the 'expr' command where appropriate. Change-Id: Ia75210c8447f88d38515addab4a836af9103096d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6161 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-08tcl: [2/3] prepare for jimtcl 0.81 'expr' syntax changeAntonio Borneo1-9/+9
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. Enclose within double quote the argument of 'expr' when there is the need to concatenate strings. Change-Id: Ic0ea990ed37337a7e6c3a99670583685b570b8b1 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6160 Tested-by: jenkins
2021-05-08tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax changeAntonio Borneo24-820/+820
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. In the TCL scripts distributed with OpenOCD there are 1700+ lines that should be modified before switching to jimtcl 0.81. Apply the script below on every script in tcl folder. It fixes more than 92% of the lines %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- #!/usr/bin/perl -Wpi my $re_sym = qr{[a-z_][a-z0-9_]*}i; my $re_var = qr{(?:\$|\$::)$re_sym}; my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i; my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)}; my $re_op = qr{<<|>>|[+\-*/&|]}; my $re_expr = qr{( (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item) \s*$re_op\s* (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\)) )}x; # [expr [dict get $regsC100 SYM] + HEXNUM] s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/; # [ expr (EXPR) ] # [ expr EXPR ] # note: $re_expr captures '$3' s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/; s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/; %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6159 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-02tcl/board: add pico-debug supportPeter Lawrence1-0/+38
pico-debug is not a board; it is a virtual CMSIS-DAP adapter that runs on the same RP2040 also being debugged. This is possible due to pico-debug running on the normally-dormant second Cortex-M0+ core (Core1), providing debugging of the first core (Core0). As such, it could be used on a variety of RP2040-based boards. Since a flash driver is useful (if not essential), a flash driver is included. This driver code originated on RPi's bespoke OpenOCD fork; lipstick was added to this particular pig to make it more presentable on OpenOCD proper. no new Clang analyzer warnings Change-Id: I31f98b5ea1664f0adfbc184b57efba963acfb958 Signed-off-by: Peter Lawrence <majbthrd@gmail.com> Reviewed-on: http://openocd.zylin.com/6075 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-04-24target/imx8qm: Initial supportLeonard Crestez1-0/+89
Chip is similar to imx8x series but has different cores at different addresses. Support for reduced versions is not yet available. Tested on imx8qm-mek board Change-Id: Ia34a80d561ab2849a570d8c375b936a45cbf45ca Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Oliver Graute <oliver.graute@kococonnector.com> Reviewed-on: http://openocd.zylin.com/5042 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-24stm32l4x: add OTP support for STM32 G0/G4/L4/L4+/L5/WB/WL devicesTarek BOCHKATI6-11/+12
this is a rework of #5320 started by Andreas then abandoned. same syntax as in stm32f2x driver: enable OTP for writing > stm32l4x otp 1 enable write to OTP > flash write_bank 1 foo.bin 0 > flash filld 0x1FFF7000 0xDeadBeafBaadF00d 1 read OTP > mdw 0x1FFF7000 4 disable OTP > stm32l4x otp 1 disable Change-Id: Id7d7c163b35d7a3f406dc200d7e2fc293b0675c2 Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5537 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-10tcl/target: add BCM2711 configuration fileTarek BOCHKATI1-0/+62
The Broadcom BCM2711 used in Raspberry Pi 4 No documentation was found on Broadcom website Partial information is available in raspberry pi website: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/ Change-Id: I3db6c9af520af8ab4c21ad35ff0f2db28efc0325 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/6066 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-10tcl/target: add BCM2837 configuration fileTarek BOCHKATI1-0/+64
This is the Broadcom chip used in the Raspberry Pi 3, and in later models of the Raspberry Pi 2. Partial information is available in raspberry pi website: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837 https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837b0 Change-Id: I1188a7866304c59f670a543809aca3927174786e Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/6069 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-10tcl/target: add BCM2836 configuration fileTarek BOCHKATI1-0/+59
The Broadcom chip used in the Raspberry Pi 2 Model B Partial information is available in raspberry pi website: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836 Change-Id: I50b040db213c5b72f63d5f5534c552426c7376f9 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/6068 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-10tcl/target: add BCM2835 configuration fileTarek BOCHKATI1-0/+24
This is the Broadcom chip used in the Raspberry Pi Model A, B, B+, the Compute Module, and the Raspberry Pi Zero. Partial information is available in raspberry pi website: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835 Change-Id: Ifeb012952473d624327e8c010ac5c886d9473aa0 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/6067 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-10tcl/target: start using the new TPIU/SWO supportAntonio Borneo3-12/+54
Create the TPIU and SWO device in target config file. Replace the target event 'trace-config' with the TPIU/SWO event 'post-enable'. Extend the existing code in the event handler to properly set the gpio mode and speed to permit synchronous trace. This patch is not exhaustive of all the targets that have SWO, but has to be considered as an initial example. Change-Id: If4bbf364c0d2aef3ae49951e76507a3b1cfd58e7 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5859 Tested-by: jenkins Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
2021-03-10tcl/target: add Rockchip RK3399 targetJiri Kastner1-0/+79
Change-Id: I28f404b1e53fc9dbb04b3f939294ae248bbde183 Signed-off-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/5994 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-10eMAG: Add Ampere eMAG config filesAnthony Ferranti1-0/+112
Add board and target configuration files for Ampere eMAG8180 board and Ampere eMAG processor. Tested on an Ampere eMAG8180 development platform. Change-Id: I222653f0fc12d25202a7e469db3594076cbc38ed Signed-off-by: Anthony Ferranti <ferranti@os.amperecomputing.com> Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Reviewed-on: http://openocd.zylin.com/5569 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-10tcl/target: Add K3 basic supportNishanth Menon1-0/+256
Add basic connection details for AM654 and J721E SoCs from TI. See AM65x Technical Reference Manual (SPRUID7, April 2018) for further details: https://www.ti.com/lit/pdf/spruid7 See J721E Technical Reference Manual (SPRUIL1, May 2019) for further details: https://www.ti.com/lit/pdf/spruil1 See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Change-Id: Ie5108c6ad6f1304a6bf5b9f81aa9ebd33b8a559d Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: http://openocd.zylin.com/5182 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2021-03-04tcl/target/eos_s3: fix variable's expansion typoAntonio Borneo1-1/+1
TCL expands the variables only if preceded by a dollar sign. Add the missing dollar before the variable's name '_CPUTAPID'. Change-Id: Icc5d0dddf24f75d12ee63fee69e1b265e842ca43 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reported-by: Wes Cilldhaire <wes@sol1.com.au> Fixes: c3166b43e415 ("tcl/target: Add QuickLogic EOS S3 MCU configuration") Reviewed-on: http://openocd.zylin.com/6079 Tested-by: jenkins Reviewed-by: TM <tommy_murphy@hotmail.com>
2020-12-26tcl/target/rk3308.cfg: add defer-examineJiri Kastner1-1/+2
only core0 is brought up by bootloader Change-Id: I1d6b5e6ba7498beadbf3805f4271f0197e411bd5 Signed-off-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/5980 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
2020-11-15tcl/target: remove deprecated ${target}_${adapter}.cfg filesTarek BOCHKATI12-23/+0
Change-Id: Ic4837ad3bd06eb353020e44638306f341a923c05 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com> Reviewed-on: http://openocd.zylin.com/5929 Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-11-15flash/stm32l4x: STM32L55/L56xx basic support (non-secure mode)Tarek BOCHKATI1-0/+130
STM32L5 have 512 Kbytes of Flash memory with dual bank architecture. STM32L5 flash is quite similar to L4 flash, mainly register names and offsets and some bits are changed. NON-SECURE flash is located at 0x8000000 like L4 devices, so no big change is needed (secure flash will be subject of another change). Note: flash driver name is set stm32l5x, in order to extend the commands with specific L5 commands (to manage TZEN for example ...) Note: this works only when TZEN=0 Change-Id: Ie758abb4aa19a3f29eeb0702d7dcb43992e4c639 Signed-off-by: Michael Jung <mijung@gmx.net> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5510 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-11-08Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interfaceAndreas Bolsch4-1/+47
- write speed up to 150 kByte/s on STM32F469I-disco (due to SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in dual 4-line mode or STM32H73BI-Disco in octal mode - tested with STM32L476G-disco (64MBit flash, 3-byte addr), STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and STM32L476G-Disco (all 128Mbit flash, 3-byte addr), STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr) STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr) STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr) STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr) - suitable cfg for Discovery boards included - limited parsing of SFDP data if flash device not hardcoded (tested only in single/quad mode as most devices either don't support SFDP at all or have empty(!) SFDP memory) - 'set' command for auto detection override (e. g. for EEPROMs) - 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.) - makefile for creation of binary loader files - tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg - tcl/board/stm32f7discovery.cfg removed as name is ambiguous (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg) - dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI with two W25Q128FV, sample cfg files included and on STM32H745I-Disco, STM32H747I-Disco, STM32H750B-Disco - read/verify/erase_check uses indirect read mode to work around silicon bug in H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last bytes causes debug interface to hang) - octospi supported only in single/dual 1-line, 2-line, 4-line and single 8-line modes, (not in hyper flash mode) Requirements: GPIOs must be initialized appropriately, and SPI flash chip be configured appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip specific, cf. included cfg files. The driver infers most parameters from current setting in CR, CCR, ... registers. Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8 Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4321 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Christopher Head <chead@zaber.com>
2020-11-07stm32h7x: Fix reset with non-HLA interfaces on macOSAlberto García Hierro1-10/+15
regsub doesn't work correctly on macOS Catalina, which results in an incorrect CHIPNAME derived from the current target. Since regsub is only used by this target, replace it with a simple string search for '.' followed by a substring. This is funcionally equivalent to what the regular expression was doing, but instead relies in simpler string operations that should have little to no differences between systems. Also, refactor CHIPNAME detection into proc stm32h7x_chipname, so it's always retrieved in the same way without duplicating the code. Change-Id: Ia9f63f56b508688e74278b022eaec47e503916e7 Signed-off-by: Alberto Garcia Hierro <alberto@garciahierro.com> Reviewed-on: http://openocd.zylin.com/5872 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-04tcl: replace '-ctibase' with '-baseaddr'Antonio Borneo11-17/+17
Replace the deprecated option '-ctibase' with the generic option '-baseaddr'. Change generated with command: sed -i 's/-ctibase/-baseaddr/g' $(find tcl/ -type f) Change-Id: If776934d2ac106532708768bb3a4ec6fcffb0368 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5870 Tested-by: jenkins
2020-11-04stm32h7x.cfg: alignment with RM0399 rev3Tarek BOCHKATI1-2/+4
in RM0399 rev2, there was these bits in DBGMCU_CR registers: - DBGSTBY_D3 : bit 7 - DBGSTOP_D3 : bit 8 these bits have been changed to reserved in rev3 Change-Id: I9d10d90e383795dc8e25a117d59fa065dc594610 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5861 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-22tcl/target/nrf52: fix nrf52_recoverTomas Vanek1-17/+18
nrf52_recover was merged in pre "Handle Tcl return values consistently" state - remove ocd_ prefixes. Erase and unlock sequence was changed to comply Nordic semiconductor recommendation: https://infocenter.nordicsemi.com/index.jsp?topic=%2Fnwp_027%2FWP%2Fnwp_027%2FnWP_027_erasing.html Change-Id: Ic54236c27cf25ad8091e9e572ba1ef846f0d47c2 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reported-by: Pieter De Gendt <pieter.degendt@gmail.com> Reviewed-on: http://openocd.zylin.com/5845 Tested-by: jenkins Reviewed-by: Pieter De Gendt <pieter.degendt@gmail.com>
2020-10-03tcl/target: Add QuickLogic EOS S3 MCU configurationJan Kowalewski1-0/+44
Add configuration for QuickLogic EOS S3 MCU target. Change-Id: I375057ff387a826e632f194843dbd92148b0c5dd Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com> Reviewed-on: http://openocd.zylin.com/5802 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-05hla_transport: split command registration per transportAntonio Borneo1-3/+4
All the HLA transports (hla_swd and hla_jtag) register the same set of commands. Such commands are mainly aimed at handling JTAG compatibility that is required for the transport hla_jtag only. Split per transport the command registration and limit the commands to only those required by the transport itself. Replace the command "hla newtap" with the transport specific "swd newdap" or "jtag newtap". Deprecate the command "hla". Change-Id: I79c78fa97b707482608516d3824151a4d07644c0 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4877 Tested-by: jenkins
2020-09-05tcl/target: use command 'jtag newtap' to add a boundary scan TAPAntonio Borneo5-6/+6
A JTAG TAP for boundary scan should be added in the scan chain through the command "jtag newtap". In some TCL target script the boundary scan TAP is added through the command "swj_newdap", command that is inappropriate in this context because specific for arm adi-v5 SWJ-DP. This situation was probably created to bypass the error with HLA framework, caused by missing command "jtag newtap". Add the command "jtag newtap" in HLA, by reusing the existing code for command "hla newtap". Fix the TCL target scripts to use the command "jtag newtap" for the boundary scan TAPs. The TCL script target/psoc6.cfg has no evident reference to HLA, so the reason for using "swj_newdap" is less clear. Nevertheless it uses the wrong command and, once HLA is fixed, there is no reason to avoid fixing it too. Change-Id: Ia92f8221430cf6f3d2c34294e22e5e18963bb88c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4873 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-08-16tcl: Add support for NDS V5 target and xc7/Corvette-F1Hellosun Wu1-0/+12
The "Corvette-F1" is an Arduino-compatible evaluation platform, which fully supports AndesCore. The board has FTDI FT2232 to connected to FPGA's JTAG interface. The "ADP-XC7KFF676" is a development and prototyping board that provides capacity for evaluation of AndesCore processors. It works with AICE in-circuit debugging tools. This patch also include target/nds32v5.cfg to support AndesCore N22/N25F and AndeShape Platform AE250. Change-Id: I144d5063d5086d00ec44634a5028b5ea5d2eba33 Signed-off-by: Hellosun Wu <wujiheng.tw@gmail.com> Reviewed-on: http://openocd.zylin.com/5338 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-08-02tcl/target/armada370: remove useless 'init' commandAntonio Borneo1-2/+0
As the comment states, the 'init' command is issued before the command 'dap apsel', otherwise it fails. This dependency has been already fixed in commit e48690cb26e4 ("target/arm_adi_v5: allow commands apsel and apcsw during init phase"), so the command 'dap apsel' can now be issued directly. Remove both the unneeded 'init' command and the comment that documents and justify its presence. Change-Id: I50f0a820fa7ead6f5a3bd9cc5180d521070822c9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5786 Tested-by: jenkins
2020-07-26tcl/target: Add initial GigaDevice GD32VF103 supportMarc Schink1-0/+26
There is no flash bank support at the moment. Change-Id: I52a2bde39425d94d9333cda002e5df0a1ef63c08 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5755 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-07-26tcl/target: add Rockchip RK3308 targetJiri Kastner1-0/+69
Change-Id: Ia8c2cec0761c37623fa8a416bcfc405f2af6a6b3 Signed-off-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/5774 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2020-07-26Introduce tcl config files for Synopsys HSDK boardEvgeniy Didin1-0/+86
With this commit we add tcl configure files for ARCv2 HS Development kit(HSDK). HSDK board has Quad-core ARC HS38 CPU with L1 and L2 caches. Change-Id: I372ef45428c7c7ca1421a6da3e5ed08b86f705e0 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5784 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-14target/icepick.cfg: Add support for Test TAPs in ICEPick CEdward Fewell1-4/+18
In addition to the debug TAPs, the ICEPick C also supports a bank of Test TAPs (limited functionality intended for non-debuggable targets). Added support for Test TAPs to the icepick_c_tapenable routine. Port numbers of 0 to 15 will continue to be handled as a debug TAP number. Test TAPs will be port numbers of 16 to 31. This functionality will be needed for doing a flash mass erase on CC26xx/CC13xx targets. It is possible for user application to block even adding the Cortex M TAP to the scan chain, so the only way to unbrick the target and erase the flash is using a component on a test TAP of the device's ICEPick router. Change-Id: I0aa52a08d43a00cbd396efdeadd504fc31c98510 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/5715 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-05-24stm8 target: make adapter speed settings workAke Rehnman2-4/+8
Previously the adapter speed settings were hard-coded to connect with low speed then switch over to high speed regardless what was mentioned in the cfg files. Now the stm8 target intercept adapter speed settings and configure the stm8 control registers accordingly. Change-Id: I7419514e5214e4b43b9d51253cf5b7f04a233533 Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com> Reviewed-on: http://openocd.zylin.com/5548 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
generated by cgit v1.1 at 2024-11-08 11:05:12 +0000