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2024-07-04Merge pull request #1082 from en-sc/en-sc/sbcs-readEvgeniy Naydanov1-20/+8
2024-07-03Merge pull request #1087 from en-sc/en-sc/delay-typesEvgeniy Naydanov3-110/+167
2024-07-03Merge pull request #1084 from en-sc/en-sc/ref-reg-filesEvgeniy Naydanov17-1486/+1678
2024-07-02target/riscv: simplify `sbcs` read in `write_memory_bus_v1()`Evgeniy Naydanov1-20/+8
2024-07-02target/riscv: separate register cache stuff into filesEvgeniy Naydanov17-1486/+1678
2024-07-01target/riscv: replace `info->*_delay` with `riscv_scan_delays`Evgeniy Naydanov3-110/+167
2024-06-25Merge up to ad87fbd1cf28760795c4e18f3318a2d720e5a8a6 from upstreamEvgeniy Naydanov11-93/+184
2024-06-23Remove other '_s' suffix from structsAntonio Borneo2-3/+3
2024-06-23Remove '_s' suffix from structsMarc Schink1-14/+14
2024-06-23itm: fix default initializationAntonio Borneo3-12/+16
2024-06-23target: aarch64: access reg SPSR_EL1 only in EL1, EL2 and EL3Antonio Borneo1-7/+15
2024-06-23target: aarch64: access reg ESR_EL1 only in EL1, EL2 and EL3Antonio Borneo1-7/+15
2024-06-23target: aarch64: access reg ELR_EL1 only in EL1, EL2 and EL3Antonio Borneo1-0/+10
2024-06-23target: aarch64: access reg SPSR_EL2 only in EL2 and EL3Antonio Borneo1-7/+15
2024-06-23target: aarch64: access reg ESR_EL2 only in EL2 and EL3Antonio Borneo1-7/+15
2024-06-23target: aarch64: access reg ELR_EL2 only in EL2 and EL3Antonio Borneo1-0/+10
2024-06-23target: aarch64: access reg SPSR_EL3 only in EL3Antonio Borneo1-7/+15
2024-06-23target: aarch64: access reg ESR_EL3 only in EL3Antonio Borneo1-9/+17
2024-06-23target: aarch64: access reg ELR_EL3 only in EL3Antonio Borneo1-0/+12
2024-06-23target: armv8_dpm: silence error on register R/WAntonio Borneo1-2/+2
2024-06-23target: aarch64: align armv8_read_reg() and armv8_read_reg32()Antonio Borneo1-4/+8
2024-06-17target: Do not use LOG_USER() for error messagesMarc Schink1-4/+3
2024-06-17target/cortex_m: allow poll quickly get out of TARGET_RESET stateTomas Vanek1-1/+5
2024-06-15target/arm_tpiu_swo: Fix memory leak on errorAntonio Borneo1-4/+2
2024-06-15fix GCC's `-Wcalloc-transposed-args` warningEvgeniy Naydanov1-2/+2
2024-06-14target/riscv: select DMI IR on batch access.Evgeniy Naydanov1-0/+2
2024-06-10Merge pull request #1073 from en-sc/en-sc/abs-reg-batchEvgeniy Naydanov3-100/+308
2024-06-08target/riscv: support for smp group manipulationParshintsev Anatoly1-0/+3
2024-06-08target: reset examine after assert_resetAntonio Borneo1-5/+7
2024-06-07Merge pull request #1044 from en-sc/en-sc/riscv-011-sep-reg-accEvgeniy Naydanov2-18/+102
2024-06-06target/riscv: write registers using batchEvgeniy Naydanov3-100/+308
2024-06-05Merge pull request #1075 from en-sc/en-sc/from_upstreamEvgeniy Naydanov13-159/+210
2024-06-04target/riscv: stop using register_get/set for 0.11 targetsEvgeniy Naydanov2-16/+102
2024-06-04Revert "Initialize all registers in examine"Evgeniy Naydanov1-2/+0
2024-06-04Merge pull request #1056 from aap-sc/aap-sc/no_hit_bit_statusAnatoly Parshintsev2-15/+90
2024-05-31riscv-013: Remove unused typedef slot_tremove-slot_t-from-riscv-013Jan Matyas1-6/+0
2024-05-30Merge up to 437dde701c13e707e5fd912ef6403e09052e4d9b from upstreamEvgeniy Naydanov13-159/+210
2024-05-28target/riscv: do not emit warnings when a non-existent CSR is hiddenParshintsev Anatoly1-1/+1
2024-05-28target/riscv: fix halt reason for targets that do not support hit bit on trig...Parshintsev Anatoly2-15/+90
2024-05-28Merge pull request #1033 from en-sc/en-sc/err-read-abs-argEvgeniy Naydanov3-80/+218
2024-05-26openocd: drop include of target_type.hAntonio Borneo2-7/+6
2024-05-26target/semihosting: Fix double free()Marc Schink1-3/+1
2024-05-26target/arm_tpiu_swo: Handle errors in pre/post-enable eventsMarc Schink1-5/+11
2024-05-26target/arm_tpiu_swo: Fix division by zeroMarc Schink1-8/+24
2024-05-23target/riscv: read abstract args using batchEvgeniy Naydanov3-80/+218
2024-05-18Merge pull request #1061 from en-sc/en-sc/dm-resetEvgeniy Naydanov1-41/+81
2024-05-17Merge pull request #1029 from MrAlexei/add_decode_wp_rvcEvgeniy Naydanov1-30/+467
2024-05-15target/riscv: only `dmactive` can be written if `dmactive` is lowEvgeniy Naydanov1-41/+81
2024-05-11target/xtensa: avoid IHI for writes to non-executable memoryIan Thompson1-8/+81
2024-05-11cortex_a: drop cortex_a_dap_write_memap_register_u32()Antonio Borneo1-52/+39
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