riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-04-26	Merge pull request #1025 from en-sc/en-sc/dump-field	Evgeniy Naydanov	5	-76/+49
2024-04-26	Merge pull request #1046 from en-sc/en-sc/reg-rv011-segfault-propper	Evgeniy Naydanov	1	-4/+4
2024-04-23	target/riscv/riscv-011: pc and dpc should be cached at the same location	Evgeniy Naydanov	1	-2/+2
2024-04-20	target/riscv/riscv-011.c: fix access to non-existent register	Evgeniy Naydanov	1	-4/+4
2024-04-19	target/riscv: decode DMI scans in batch access	Evgeniy Naydanov	5	-76/+49
2024-04-14	Merge pull request #1040 from rivos-eblot/dev/ebl/read_mem_dmibase	Evgeniy Naydanov	1	-1/+5
2024-04-14	Merge pull request #1023 from en-sc/en-sc/check-ac-busy	Evgeniy Naydanov	1	-80/+239
2024-04-14	Merge pull request #1039 from en-sc/en-sc/running-cache	Evgeniy Naydanov	1	-1/+2
2024-04-11	target/riscv: check `abstractcs.busy`	Evgeniy Naydanov	1	-6/+73
2024-04-11	target/riscv: introduce `examine_dm()` function	Evgeniy Naydanov	1	-73/+131
2024-04-10	target/riscv: cache `abstractcs.busy` in `dm013_info_t`	Evgeniy Naydanov	1	-2/+36
2024-04-05	target/riscv: read registers are not valid on a running target	Evgeniy Naydanov	1	-1/+2
2024-04-04	target/riscv: Add missing DM base offset to read_memory_bus_v1()	Emmanuel Blot	1	-1/+5
2024-03-28	Merge up to a35e254c5383008cdacf7838a777f7f17af5eeb1 from upstream	Evgeniy Naydanov	11	-61/+748
2024-03-24	target/adi_v5_swd: move setting of do_reconnect one level up	Tomas Vanek	1	-12/+10
2024-03-24	helper/list: include the correct header file	Antonio Borneo	1	-0/+1
2024-03-21	[NFC] target/riscv: refactor `init_registers()`	Evgeniy Naydanov	3	-379/+529
2024-03-16	target/mips32: add fpu access support	Walter Ji	4	-12/+245
2024-03-16	target: aarch64: add support for 32 bit MON mode	Antonio Borneo	1	-0/+3
2024-03-16	target/adi_v5_swd: fix DP registers banking	Tomas Vanek	1	-6/+9
2024-03-16	target/arm_adi_v5: introduce adiv5_jim_configure_ext()	Tomas Vanek	4	-26/+29
2024-03-09	target/mips32: add dsp access support	Walter Ji	2	-1/+447
2024-03-09	mem_ap: fix GDB connections	Antonio Borneo	1	-4/+4
2024-03-07	Merge up to 07141132a7d787005c0829618a60b4a842be7847 from upstream	Evgeniy Naydanov	4	-71/+74
2024-03-02	target/esp_xtensa_smp: don't use coreid as an SMP index	Erhan Kurubas	1	-2/+5
2024-02-27	Merge pull request #977 from kr-sc/kr-sc/improve-riscv-controls	Evgeniy Naydanov	2	-80/+68
2024-02-24	src/target/riscv: Help older compilers	Sevan Janiyan	1	-1/+1
2024-02-24	Merge pull request #1018 from en-sc/en-sc/from_upstream	Evgeniy Naydanov	1	-36/+12
2024-02-21	Merge pull request #1014 from riscv-collab/riscv-batch-cleanup	Evgeniy Naydanov	5	-82/+93
2024-02-16	Merge pull request #1016 from tom-van/free-dm-target_list	Evgeniy Naydanov	1	-0/+25
2024-02-15	Fixes of review findingsriscv-batch-cleanup	Jan Matyas	1	-3/+7
2024-02-15	portability fix: Switch binary literals to hex	Sevan Janiyan	2	-68/+68
2024-02-15	Merge up to efdd5e09b1108e3bd35898a684817c01dc95cd93 from upstream	Evgeniy Naydanov	1	-36/+12
2024-02-13	target/riscv: Improve riscv controls that manage the set of available trigger...	Kirill Radkin	2	-80/+68
2024-02-12	Merge pull request #1011 from en-sc/en-sc/wa-halt-groups	Jan Matyas	1	-0/+6
2024-02-11	target/cortex_m: fix couple of comments	Tomas Vanek	1	-8/+6
2024-02-11	target/cortex_m: drop useless target_halt() call	Tomas Vanek	1	-27/+4
2024-02-11	target/cortex_m: prevent asserting reset if examine is deferred	Tomas Vanek	1	-1/+2
2024-02-11	target/riscv: free dm and target_list structures	Tomas Vanek	1	-0/+25
2024-02-09	Merge pull request #1013 from riscv/dm-calls-cleanup	Jan Matyas	1	-10/+11
2024-02-09	Merge pull request #1008 from en-sc/en-sc/from_upstream	Jan Matyas	14	-76/+107
2024-02-06	riscv/program: Removed dead code for restoring register values	Jan Matyas	2	-23/+0
2024-02-06	Fixes and cleanup in riscv batch and related functions	Jan Matyas	5	-81/+88
2024-02-05	Cosmetic cleanup of dm_*() calls in riscv-013.c	Jan Matyas	1	-10/+11
2024-02-02	target/riscv: set `state` and `debug_reason` in `riscv_halt_go_all_harts()`	Evgeniy Naydanov	1	-0/+6
2024-01-29	Merge pull request #1006 from en-sc/en-sc/break-ll-revert	Jan Matyas	6	-40/+1
2024-01-29	Merge up to 9659a9b5e28dc615dfb508d301fdd8fa426c191b from upstream	Evgeniy Naydanov	14	-76/+107
2024-01-29	target/mips32: fix false positive from clang	Antonio Borneo	1	-8/+9
2024-01-29	target/xtensa: enable xtensa algo support	ianst	3	-4/+23
2024-01-29	target: drop deprecated code for mem2array and array2mem	Antonio Borneo	2	-441/+35