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2009-09-20Debug message updates:dbrownell1-12/+1
2009-09-19Added CPUDBG_WCR_BASE definemlu1-0/+1
2009-09-19Avoid cache invalidation when writing to hardware debug registersmlu1-4/+19
2009-09-19Minor behavior fixes for the two JTAG reset events (C/internal,dbrownell1-1/+2
2009-09-18Move Cortex A8 debug access initialisation from omap3530.cfg to cortex_a8.cmlu1-28/+39
2009-09-17srst_gates_jtag option. at91sam9260 needs retesting, and possibly srst_gates_...oharboe1-1/+12
2009-09-17The "arm9tdmi.c" file is more of a generic ARM9 support file:dbrownell1-3/+17
2009-09-16Remove unused varables (moved to armv7a)mlu1-5/+0
2009-09-16Use a variable armv7a->debug_base instead of hardedcoded OMAP3530_DEBUG_BASEmlu1-28/+31
2009-09-15Define debug_base, debug_ap, memory_ap in armv7a_common_tmlu1-0/+7
2009-09-15Updated mode string list.mlu1-2/+2
2009-09-15Definy symbolic values for VA to PA address translation operationsmlu1-0/+10
2009-09-14Check return values to avoid infinite wait in loop on error.mlu1-4/+8
2009-09-14Cache invalidation when writing to memorymlu1-0/+18
2009-09-13More CortexA8 debug register definitions.mlu1-0/+4
2009-09-13Fix argument passing in cortex_a8_write_cp.mlu1-2/+1
2009-09-12David Brownell <david-b@pacbell.net> oharboe3-26/+40
2009-09-11Nicolas Pitre <nico@cam.org> put feroceon target definition at the end so to ...oharboe1-86/+79
2009-09-11Nicolas Pitre <nico@cam.org> Dragonite supportoharboe4-20/+76
2009-09-11spelling mistakeoharboe1-2/+2
2009-09-11do not use dynamically sized stack arrays, not compatible with embedded OS'soharboe1-10/+24
2009-09-11registering a target event twice caused infinite loop. Same bug as in jtag/co...oharboe1-4/+9
2009-09-11Nicolas Pitre <nico@cam.org> tighten error checking in bulk_writeoharboe1-4/+15
2009-09-10Alexei Babich <a.babich@rez.ru> fix problems with unecessary tailend byte acc...oharboe1-0/+12
2009-09-09David Brownell <david-b@pacbell.net> oharboe4-4/+20
2009-09-08Report correct core instruction state for ARMv/A targetsmlu1-1/+1
2009-09-08Load PC with bit 0 set to 1 when resuming to say in Thumb instruction state.mlu1-2/+7
2009-09-08David Brownell <david-b@pacbell.net> oharboe1-0/+86
2009-09-08David Brownell <david-b@pacbell.net> oharboe1-35/+137
2009-09-07Improved handling of instruction set state, helps for debugging Thumb state.mlu1-7/+5
2009-09-04Mahr, Stefan <Stefan.Mahr@sphairon.com> removes the endianness swapping in mi...oharboe1-44/+0
2009-09-04Matt Hsu <matt@0xlab.org> This patch simply enables the halting debug mode.oharboe1-0/+7
2009-09-04more debug output for breakpointsoharboe1-2/+10
2009-09-04Matt Hsu <matt@0xlab.org> Tidy up the bit-offset operation for DSCR registeroharboe2-6/+15
2009-09-01- fix a regression when using cortex_m3 emulated dcc channelntfreak1-10/+19
2009-08-31Warning fixduane1-0/+3
2009-08-30David Brownell <david-b@pacbell.net> start phasing out integers as target IDsoharboe2-35/+22
2009-08-28David Brownell <david-b@pacbell.net> fix warningsoharboe1-4/+8
2009-08-28added arm11 timeout error messagesoharboe3-11/+94
2009-08-28restore ICE watchpoint registers when the *last* software breakpoint is removedoharboe2-3/+23
2009-08-28David Brownell <david-b@pacbell.net> ARM disassembly support for about five d...oharboe1-6/+345
2009-08-27arm11 hardware step using simulation + breakpoint. Use "hardware_step enable"...oharboe1-19/+28
2009-08-27arm11 single stepping wip - at least we know the next PC nowoharboe1-0/+4
2009-08-27arm11 single stepping wipoharboe1-0/+101
2009-08-27refactor arm simulator to allow arm11 code to use it as well - no observable ...oharboe2-49/+147
2009-08-26Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ...oharboe1-5/+23
2009-08-26Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ...oharboe1-1/+1
2009-08-26Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> ...oharboe1-1/+1
2009-08-26Matt Hsu <matt@0xlab.org> cortex-a8: Copy some more registers from the docume...oharboe1-0/+8
2009-08-26Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instructio...oharboe1-1/+9
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